ISL78223 Datasheet, PDF (5/20 Pages) Intersil Corporation – ZVS Full-Bridge PWM Controller with Adjustable Synchronous Rectifier Control

Pin Configuration
Pin Descriptions
PIN NUMBER
1
SYMBOL
VREF
2
VERR
3
CTBUF
4
RTD
5
RESDEL
6
CT
7
FB
8
RAMP
9
CS
ISL78223
ISL78223
(20 LD QSOP)
TOP VIEW
VREF 1
VERR 2
CTBUF 3
RTD 4
RESDEL 5
CT 6
FB 7
RAMP 8
CS 9
IOUT 10
20 SS
19 VADJ
18 VDD
17 OUTLL
16 OUTLR
15 OUTUL
14 OUTUR
13 OUTLLN
12 OUTLRN
11 GND
DESCRIPTION
The 5.00V reference voltage output having 3% tolerance over line, load and operating temperature.
Bypass to GND with a 0.1µF to 2.2µF low ESR capacitor.
The control voltage input to the inverting input of the PWM comparator. The output of an external error
amplifier (EA) is applied to this input, either directly or through an opto-coupler, for closed loop regulation.
VERR has a nominal 1mA pull-up current source.
When VERR is driven by an opto-coupler or other current source device, a pull-up resistor from VREF is
required to linearize the gain. Generally, a pull-up resistor on the order of 5kΩ is acceptable.
CTBUF is the buffered output of the sawtooth oscillator waveform present on CT and is capable of sourcing
2mA. It is offset from ground by 0.40V and has a nominal valley-to-peak gain of 2. It may be used for slope
compensation.
This is the oscillator timing capacitor discharge current control pin. The current flowing in a resistor
connected between this pin and GND determines the magnitude of the current that discharges CT. The
CT discharge current is nominally 20x the resistor current. The PWM deadtime is determined by the
timing capacitor discharge duration. The voltage at RTD is nominally 2.00V.
Sets the resonant delay period between the toggle of the upper FETs and the turn on of either of the lower
FETs. The voltage applied to RESDEL determines when the upper FETs switch relative to a lower FET
turning on. Varying the control voltage from 0 to 2.00V increases the resonant delay duration from 0 to
100% of the deadtime. The control voltage divided by 2 represents the percent of the deadtime equal to
the resonant delay. In practice the maximum resonant delay must be set lower than 2.00V to ensure that
the lower FETs, at maximum duty cycle, are OFF prior to the switching of the upper FETs.
The oscillator timing capacitor is connected between this pin and GND. It is charged through an internal
200μA current source and discharged with a user adjustable current source controlled by RTD
FB is the inverting inputs to the error amplifier (EA). The amplifier may be used as the error amplifier for
voltage feedback or used as the average current limit amplifier (IEA). If the amplifier is not used, FB
should be grounded.
This is the input for the sawtooth waveform for the PWM comparator. The RAMP pin is shorted to GND at
the termination of the PWM signal. A sawtooth voltage waveform is required at this input. For
current-mode control this pin is connected to CS and the current loop feedback signal is applied to both
inputs. For voltage-mode control, the oscillator sawtooth waveform may be buffered and used to generate
an appropriate signal, RAMP may be connected to the input voltage through a RC network for voltage feed
forward control, or RAMP may be connected to VREF through a RC network to produce the desired
sawtooth waveform.
This is the input to the overcurrent comparator. The overcurrent comparator threshold is set at 1.00V
nominal. The CS pin is shorted to GND at the termination of either PWM output.
Depending on the current sensing source impedance, a series input resistor may be required due to the
delay between the internal clock and the external power switch. This delay may result in CS being
discharged prior to the power switching device being turned off.
5
FN7936.1
January 2, 2013