ISL78223 Datasheet, PDF (6/20 Pages) Intersil Corporation – ZVS Full-Bridge PWM Controller with Adjustable Synchronous Rectifier Control

ISL78223
Pin Descriptions (Continued)
PIN NUMBER
10
11
13, 12
15, 14
17, 16
18
19
20
SYMBOL
IOUT
GND
OUTLLN, OUTLRN
OUTUL, OUTUR
OUTLL, OUTLR
VDD
VADJ
SS
DESCRIPTION
Output of the 4X buffer amplifier of the sample and hold circuitry that captures and averages the CS
signal.
Signal and power ground connections for this device. Due to high peak currents and high frequency
operation, a low impedance layout is necessary. Ground planes and short traces are highly
recommended.
These outputs are the complements of the PWM (lower) bridge FETs. OUTLLN is the complement of OUTLL
and OUTLRN is the complement of OUTLR. These outputs are suitable for control of synchronous
rectifiers. The phase relationship between each output and its complement is controlled by the voltage
applied to VADJ.
These outputs control the upper bridge FETs and operate at a fixed 50% duty cycle in alternate sequence.
OUTUL controls the upper left FET and OUTUR controls the upper right FET. The left and right designation
may be switched as long as they are switched in conjunction with the lower FET outputs, OUTLL and
OUTLR.
These outputs control the lower bridge FETs, are pulse width modulated, and operate in alternate
sequence. OUTLL controls the lower left FET and OUTLR controls the lower right FET. The left and right
designation may be switched as long as they are switched in conjunction with the upper FET outputs,
OUTUL and OUTUR.
V_DD is the power connection for the IC. To optimize noise immunity, bypass V_DD to GND with a ceramic
capacitor as close to the V_DD and GND pins as possible.
VDD is monitored for supply voltage undervoltage lock-out (UVLO). The start and stop thresholds track
each other resulting in relatively constant hysteresis.
A 0V to 5V control voltage applied to this input sets the relative delay or advance between OUTLL/OUTLR
and OUTLLN/OUTLRN. The phase relationship between OUTUL/OUTUR and OUTLL/OUTLR is maintained
regardless of the phase adjustment between OUTLL/OUTLR and OUTLLN/OUTLRN.
The range of phase delay/advance is either zero or 40 to 300ns with the phase differential increasing as
the voltage deviation from 2.5V increases. The relationship between the control voltage and phase
differential is non-linear. The gain (Δt/ΔV) is low for control voltages near 2.5V and rapidly increases as
the voltage approaches the extremes of the control range. This behavior provides the user increased
accuracy when selecting a shorter delay/advance duration.
When the PWM outputs are delayed relative to the SR outputs (VADJ < 2.425V), the delay time should not
exceed 90% of the deadtime as determined by RTD and CT.
Connect the soft-start timing capacitor between this pin and GND to control the duration of soft-start. The
value of the capacitor and the internal current source determine the rate of increase of the duty cycle
during start-up.
SS may also be used to inhibit the outputs by grounding through a small transistor in an open
collector/drain configuration.
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL78223AAZ
78223 AAZ
-40 to +105
20 Ld QSOP
M20.15
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL78223. For more information on MSL, please see tech brief TB363.
6
FN7936.1
January 2, 2013