ISL70002SEH Datasheet, PDF (9/23 Pages) Intersil Corporation – Rad Hard and SEE Hard 12A Synchronous Buck Regulator with Multi-Phase Current Sharing

ISL70002SEH
Electrical Specifications Unless otherwise noted, V_IN = AVDD = DVDD = PVINx = EN = FSEL = M/S = SC0 = SC1= 3V to 5.5V;
GND = AGND = DGND = PGNDx = ISHx = ISHCOM = ISHEN = ISHREFx = ISHSL = TDI = TDO = TPGM = 0V; FB = 0.65V; PORSEL = V_IN for 4.5V ≤
V_IN ≤ 5.5V and GND for V_IN < 4.5V; LXx = SYNC = Open Circuit; OCx is connected to OCSSx with a 10kΩ resistor; OCx is connected to GND with
a 4.99kΩ resistor shunted by a 6.8nF capacitor; PGOOD is pulled up to V_IN with a 1kΩ resistor; REF is bypassed to GND with a 220nF capacitor;
SS is bypassed to GND with a 100nF capacitor; T_A = T_J = -55°C to +125°C; Post 100krad(Si). (Note 6). (Continued)
PARAMETER
TEST CONDITIONS
MIN
(Note 10) TYP
MAX
(Note 10)
UNITS
Output Voltage Tolerance
V_OUT = 0.8V to 2.5V, I_OUT = 0A to 12A (Notes 11, 12)
-2
Error Amp Input Offset Voltage
V_IN = 5.5V, V_REF = 600mV, Test Mode
-1
Feedback (FB) Input Leakage Current
V_IN = 5.5V, V_FB = 600mV
-1.5
Sustained Output Current
V_IN = 3V, V_OUT = 1.8V, OCA = OCB = PVIN (Note 13)
16
22
PWM CONTROL LOGIC
2
%
3
mV
1.5
µA
A
Internal Oscillator Tolerance
External Oscillator Range
FSEL = V_IN or GND
M/S = GND
-15
15
%
0.4
1.2
MHz
Minimum LXx On Time
Minimum LXx Off Time
Minimum LXx On Time
Minimum LXx Off Time
PORSEL, Master/Slave (M/S), SC1, SC0,
ISHSL, ISHEN, FSEL Input Voltage
V_IN = 5.5V, Test Mode
V_IN = 5.5V, Test Mode
V_IN = 3V, Test Mode
V_IN = 3V, Test Mode
Input High Threshold
Input Low Threshold
200
275
ns
0
50
ns
225
300
ns
0
50
ns
V_IN -0.5
1.3
V
1.2
0.5
V
PORSEL, Master/Slave (M/S), SC1, SC0,
V_IN = 5.5V
ISHSL, ISHEN, FSEL Input Leakage Current
-1
1
µA
Synchronization (SYNC) Input Voltage
Input High Threshold, M/S = GND
2.3
1.7
V
Input Low Threshold, M/S = GND
1.5
1
V
Synchronization (SYNC) Input Leakage
V_IN = 5.5V, M/S = GND, SYNC = V_IN or GND
-1
Current
1
µA
Synchronization (SYNC) Output Voltage
POWER BLOCKS
V_IN - V_OH @ I_OH = -1mA
V_OL@ I_OL = 1mA
0.1
0.4
V
0.1
0.4
V
Upper Device r_DS(ON)
V_IN = 3V, 4A load, All Power Blocks in Parallel,
Test Mode (Note 9)
20
40
mΩ
Lower Device r_DS(ON)
V_IN = 3V, 4A load, All Power Blocks in Parallel,
Test Mode (Note 9)
15
30
mΩ
LXx Output Leakage
Deadtime (Note 12)
V_IN = 5.5V, EN = LXx = GND, Single LXx Output
-1
V_IN = LXx = 5.5V, EN = GND, Single LXx Output
Within a Single Power Block or between Power Blocks 2.2
25
µA
10
µA
ns
Efficiency (Note 12)
POWER-ON RESET
V_IN = 3.3V, V_OUT = 1.8V, I_OUT = 6A, FSEL = GND
V_IN = 5V, V_OUT = 2.5V, I_OUT = 6A
88
%
90
%
VIN POR
Rising Threshold, PORSEL = V_IN
Hysteresis, PORSEL = V_IN
Rising Threshold, PORSEL = GND
4.1
4.3
4.45
V
225
325
425
mV
2.65
2.8
2.95
V
Hysteresis, PORSEL = GND
70
140
240
mV
Enable (EN) Input Voltage
Rising/Falling Threshold
0.56
0.6
0.64
V
Enable (EN) Input Leakage Current
V_IN = 5.5V, EN = V_IN or GND
-3
3
µA
9
FN8264.1
April 5, 2012