ISL70002SEH Datasheet, PDF (18/23 Pages) Intersil Corporation – Rad Hard and SEE Hard 12A Synchronous Buck Regulator with Multi-Phase Current Sharing

ISL70002SEH
the total output capacitance and ΔI_L(P-P) is the peak to peak ripple
current in the output inductor.
L_OUT
≤
2-----⋅_{---C-----O----U-----T----}⋅_{---V-----O----U----T--}
(ΔI_STEP)²
ΔV_MAX – (ΔI_L(P-P) ⋅ ESR)
(EQ. 11)
L_O
U
T
≤
---2-----^â‹---C----^O-----^U----^T----
(ΔI_STEP)²
ΔV_MAX – (ΔI_L(P-P) ⋅ ESR)
⎛
⎝
V_I
N
–
V _{O U T⎠⎞}
(EQ. 12)
The other concern when selecting an output inductor is to insure
there is adequate slope compensation when the regulator is
operated above 40% duty cycle. In most cases, the maximum
slope compensation setting (SC1 = DVDD, SC0 = DVDD provides
sufficient phase margin, therefore this is the recommended
configuration.
Input Capacitor Selection
Input capacitors are responsible for sourcing the AC component
of the input current flowing into the switching power devices.
Their RMS current capacity must be sufficient to handle the AC
component of the current drawn by the switching power devices
which is related to duty cycle. The maximum RMS current
required by the regulator is closely approximated by Equation 13.
IRMS = IOUT ×
V_{-----O-----U-----T--}
VIN
1
+
-¹--
3
×
⎛
⎜
⎝
I^--_O^------_U^-V---_T^--I--N--×^----–-L^---V-_O^---O--_U^---U--_T^---T--×^-----f^--_s^--
×
V_{----V-O---I--UN-----T--⎠⎟⎞}
2
(EQ. 13)
The important parameters to consider when selecting an input
capacitor are the voltage rating and the RMS ripple current
rating. For reliable operation, select capacitors with voltage
ratings at least 1.5x greater than the maximum input voltage.
The capacitor RMS ripple current rating should be higher than
the largest RMS ripple current required by the circuit.
A combination of low ESR tantalum capacitors and ceramic
capacitors with X7R dielectric are recommended. The
ISL70002SEH requires a minimum effective input capacitance
of 100µF for stable operation.
PCB Design
PCB design is critical to high-frequency switching regulator
performance. Careful component placement and trace routing
are necessary to reduce voltage spikes and minimize
undesirable voltage drops. Selection of a suitable thermal
interface material is also required for optimum heat dissipation
and to provide lead strain relief.
PCB Plane Allocation
Four layers of two ounce copper are recommended. Layer 2
should be a dedicated ground plane with all critical component
ground connections made with vias to this layer. Layer 3 should
be a dedicated power plane split between the input and output
power rails. Layers 1 and 4 should be used primarily for signals,
but can also provide additional power and ground islands as
required.
PCB Component Placement
Components should be placed as close as possible to the IC to
minimize stray inductance and resistance. Prioritize the
placement of bypass capacitors on the pins of the IC in the order
shown: REF, SS, AVDD, DVDD, PVINx (high frequency capacitors),
EN, PGOOD, PVINx (bulk capacitors).
Locate the output voltage resistive divider as close as possible to
the FB pin of the IC. The top leg of the divider should connect
directly to the POL (Point Of Load) and the bottom leg of the
divider should connect directly to AGND. The junction of the
resistive divider should connect directly to the FB pin.
A small series R-C snubber connected from the LXx pins to the
PGNDx pins may be used to damp high frequency ringing on the
LXx pins if desired.
PCB Layout
Use a small island of copper to connect the LXx pins of the IC to
the output inductor on layers 1 and 4. Void the copper on layers 2
and 3 adjacent to the island to minimize capacitive coupling to
the power and ground planes. Place most of the island of layer 4
to minimize the amount of copper that must be voided from the
ground plane (layer 2).
Keep all other signal traces as short as possible.
For an example layout refer to AN1732.
Thermal Management
For optimum thermal performance, place a pattern of vias on the
top layer of the PCB directly underneath the IC. Connect the vias
to the ground plane on layer 2, which serves as a heatsink. To
insure good thermal contact, thermal interface material such as
a Sil-Pad or thermally conductive epoxy should be used to fill the
gap between the vias and the bottom of the IC.
Lead Strain Relief
The package leads protrude from the bottom of the package and
the leads are slightly bent to provide strain relief.
18
FN8264.1
April 5, 2012