ISL70002SEH Datasheet, PDF (17/23 Pages) Intersil Corporation – Rad Hard and SEE Hard 12A Synchronous Buck Regulator with Multi-Phase Current Sharing

ISL70002SEH
comparator trips on two consecutive switching cycles, indicating
a valid undervoltage condition, the undervoltage protection logic
shuts down the regulator. If the feedback voltage rises back
above the undervoltage threshold plus a specified amount of
hysteresis outlined in the “Electrical Specifications” table on
page 10 after the first detection and before the second, normal
operation continues.
After the regulator shuts down, it enters a delay interval,
equivalent to the selected soft-start interval. The undervoltage
counter is reset entering the delay interval. The protection logic
initiates a normal soft-start once the delay interval ends. If the
output successfully soft-starts, the power-good signal goes high
and normal operation continues. If undervoltage conditions
continue to exist during the soft-start interval, the undervoltage
counter must overflow before the regulator shuts down again.
This hiccup mode continues indefinitely until the output soft-
starts successfully.
Overcurrent Protection
A pilot devices integrated into the PMOS transistor of Power Blocks
2 and 6 samples the inductor current each cycle. This current
feedback is scaled and compared to an overcurrent threshold
based on the overcurrent resistor connected from OCx to AGND.
If the sampled current exceeds the overcurrent threshold, an
overcurrent counter increments. If the sampled current falls below
the threshold before the counter overflows, the counter is reset.
Once the overcurrent counter reaches 2, the regulator shuts down.
After the regulator shuts down, it enters a delay interval,
equivalent to the soft-start interval, allowing the device to cool.
The overcurrent counter is reset entering the delay interval. The
protection logic initiates a normal soft-start once the delay
interval ends. If the output successfully soft-starts, the power-
good signal goes high and normal operation continues. If
overcurrent conditions continue to exist during the soft-start
interval, the overcurrent counter must overflow before the
regulator shut downs the output again. This hiccup mode
continues indefinitely until the output soft-starts successfully.
Component Selection Guide
This design guide is intended to provide a high-level explanation
of the steps necessary to create a power converter. It is assumed
the reader is familiar with many of the basic skills and
techniques referenced below. In addition to this guide, Intersil
provides a complete evaluation board that includes schematic,
BOM, and an example PCB layout.
Output Filter Design
The output inductor and the output capacitor bank together form
a low-pass filter responsible for smoothing the pulsating voltage
at the phase node. The filter must also provide the transient
energy until the regulator can respond. Since the filter has low
bandwidth relative to the switching frequency, it limits the
system transient response. The output capacitors must supply or
sink current while the current in the output inductor increases or
decreases to meet the load demand.
OUTPUT CAPACITOR SELECTION
The critical load parameters in choosing the output capacitors are
the maximum size of the load step (ΔI_STEP), the load-current slew
17
rate (di/dt), and the maximum allowable output voltage deviation
under transient loading (ΔV_MAX). Capacitors are characterized
according to their capacitance, ESR (Equivalent Series Resistance)
and ESL (Equivalent Series Inductance).
At the beginning of a load transient, the output capacitors supply all
of the transient current. The output voltage will initially deviate by an
amount approximated by the voltage drop across the ESL. As the
load current increases, the voltage drop across the ESR increases
linearly until the load current reaches its final value. Neglecting the
contribution of inductor current and regulator response, the output
voltage initially deviates by an amount shown in Equation 8.
ΔV_MAX ≈
E
SL
×
-^d---ⁱ
dt
+ [ESR × ΔI_STEP]
(EQ. 8)
The filter capacitors selected must have sufficiently low ESL and
ESR such that the total output voltage deviation is less than the
maximum allowable ripple.
Most capacitor solutions rely on a mixture of high frequency
capacitors with relatively low capacitance in combination with
bulk capacitors having high capacitance but larger ESR.
Minimizing the ESL of the high-frequency capacitors allows them
to support the output voltage as the current increases.
Minimizing the ESR of the bulk capacitors allows them to supply
the increased current with less output voltage deviation.
Ceramic capacitors with X7R dielectric are recommended.
Alternately, a combination of low ESR solid tantalum capacitors
and ceramic capacitors with X7R dielectric may be used.
The ESR of the bulk capacitors is responsible for most of the
output voltage ripple. As the bulk capacitors sink and source the
inductor AC ripple current, a voltage, V_P-P(MAX), develops across
the bulk capacitor according to Equation 9.
V_P-P(MAX) = ESR ×
(_---V_{----I--N-----–-----}V_{----O-----U----T---})_---V_{----O-----U----T-}
L_OUT × f_s × V_IN
(EQ. 9)
OUTPUT INDUCTOR SELECTION
Once the output capacitors are selected, the maximum allowable
ripple voltage, V_P-P(MAX), determines the lower limit on the
inductance as shown in Equation 10.
L_OUT ≥ ESR × -_f⁽-_s--^V---_×-^I--^N-_V----–-_I-_N---^V---_×-^O----_V^U----_PT---_--⁾-_P--^V--₍-_M-^O----_AU---_X-^T---₎
(EQ. 10)
Since the output capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the transient,
the capacitor voltage becomes slightly depleted. The output
inductor must be capable of assuming the entire load current
before the output voltage decreases more than ΔV_MAX. This
places an upper limit on inductance.
Equation 11 gives the upper limit on output inductance for the
case when the trailing edge of the current transient causes the
greater output voltage deviation than the leading edge. Equation
12 addresses the leading edge. Normally, the trailing edge
dictates the inductance selection because duty cycles are usually
<50%. Nevertheless, both inequalities should be evaluated, and
inductance should be governed based on the lower of the two
results. In each equation, L_OUT is the output inductance, C_OUT is
FN8264.1
April 5, 2012