ISL70002SEH Datasheet, PDF (5/23 Pages) Intersil Corporation – Rad Hard and SEE Hard 12A Synchronous Buck Regulator with Multi-Phase Current Sharing

ISL70002SEH
Pin Descriptions (Continued)
PIN NUMBER
22
23, 28, 32, 37, 38,
43, 44, 49, 53, 58
24, 27, 33, 36, 39,
42, 45, 48, 54, 57
25, 26, 34, 35, 40,
41, 46, 47, 55, 56
29
30
31, 50
51, 52
PIN NAME
SYNC
PVINx
LXx
PGNDx
M/S
FSEL
NC
SC0/1
DESCRIPTION
When SYNC is configured as an output (clock Master Mode, M/S = DVDD), this pin drives the SYNC input of
another ISL70002SEH with a square ware that is inverted (~180° out-of-phase) from the Master clockdriving
the Master PWM circuits. When configured as an input (clock Slave Mode, M/S = DGND), this pin uses the SYNC
output from another ISL70002SEH or an external clock to drive the clock Slave PWM circuitry. If synchronizing
to an external clock, the clock must be SEE hardened and the frequency must be within the range of 400kHz
to 1.2MHz.
These pins are the power supply inputs to the corresponding internal power blocks. These pins must be
connected to a common power supply rail, which must fall in the range of 3V to 5.5V. Bypass these pins directly
to PGNDx with ceramic capacitors located as close as possible to the IC. PVINx should be the same voltage as
DVDD and AVDD (±200mV).
These pins are the outputs of the corresponding internal power blocks and should be connected to the output
filter inductor. Internally, these pins are connected to the synchronous MOSFET power switches.
These pins are the power grounds associated with the corresponding internal power blocks. These pins also
provide the ground path for the metal package lid. Connect these pins directly to the PCB ground plane. These
pins should also connect to the negative terminals of the input and output capacitors. Locate the input and
output capacitors as close as possible to the IC.
This pin is the clock Master/Slave input for selecting the direction of the bi-directional SYNC pin. For
SYNC = Output (Master Mode), connect this pin to DVDD. For SYNC = Input (Slave Mode), connect this pin to the
PCB ground plane.
This pin is the oscillator frequency select input. Tie this pin to DVDD to select a 1MHz nominal oscillator
frequency. Tie this pin to the PCB ground plane to select a 500kHz nominal oscillator frequency.
These are No Connect pins that are not connected to anything internally. They should be connected to the PCB
ground plane.
These pins are inputs that comprise a 2-bit code to select the slope compensation (SC) current ramp referred
to the output as shown below.
SC1 = DVDD, SC0 = DVDD: SC = 6.6A/µs for FSEL = DGND
SC1 = DVDD, SC0 = DGND: SC = 3.3A/µs for FSEL = DGND
SC1 = DGND, SC0 = DVDD: SC = 1.6A/µs for FSEL = DGND
SC1 = DGND, SC0 = DGND: SC = 0.8A/µs for FSEL = DGND
SC1 = DVDD, SC0 = DVDD: SC= 13.4A/µs for FSEL = DVDD
SC1 = DVDD, SC0 = DGND: SC = 6.7A/µs for FSEL = DVDD
SC1 = DGND, SC0 = DVDD: SC = 3.4A/µs for FSEL = DVDD
SC1 = DGND, SC0 = DGND: SC = 1.7A/µs for FSEL = DVDD
59
60, 62
61, 63
64
EN
OCSSB/A
OCB/A
REF
If using current share, SC0 and SC1 of the Slave MUST match the Master SC0 and SC1.
This pin is the enable input to the IC. This is a comparator type input with a rising threshold of 0.6V and
programmable hysteresis. Driving this pin above 0.6V enables the IC. Bypass this pin to the PCB ground plane
with a 10nF ceramic capacitor to mitigate SEE.
This pin is a switch to AGND that is active during the soft-start period. It is used to set the redundant A/B peak
overcurrent limit threshold during soft-start. Connect a resistor from OCSSx to OCx in accordance with the
following equation: ROCSSx 600mV / [(IOCSSx - IOCx) /100,000]
where IOCx is the desired peak overcurrent limit during normal operation and IOCSSx is the desired peak
current limit threshold during soft-start.
This pin is a source follower output that is used to set the redundant A/B peak overcurrent limit threshold during
normal operation. Connect a resistor from this pin to the PCB ground plane in accordance with the following
equation: ROCx = 600mV / (IOCx /100,000), where IOCx is the desired peak current limit threshold during
normal operation.
This pin is the internal reference voltage output. Bypass this pin to the PCB ground plane with a 220nF ceramic
capacitor located as close as possible to the IC. The bypass capacitor is needed to mitigate SEE. No current
(sourcing or sinking) is available from this pin.
If using current share, tie REF of the Master to REF of the Slave through a 10Ω resistor.
5
FN8264.1
April 5, 2012