ISL70002SEH Datasheet, PDF (15/23 Pages) Intersil Corporation – Rad Hard and SEE Hard 12A Synchronous Buck Regulator with Multi-Phase Current Sharing

ISL70002SEH
appears on the SYNC pin. To synchronize the regulator to the
SYNC output of another ISL70002SEH regulator or to an SEE
hardened external clock, connect the M/S pin to DGND. In this
case the SYNC pin is an input that accepts an external
synchronizing signal. When M/S is connected to DGND, the
ISL70002SEH is synchronized 180° out-of-phase with respect to
the SYNC input of a Master configured regulator SYNC output or
to an external clock.
Two Phase Operation
The ISL70002SEH is capable of operating 2 ICs as a single Two
Phase regulator with nearly twice the load current capacity. In
this mode, a redundant Current Sharing bus balances the load
current between the two devices and communicates any fault
conditions. One ISL70002SEH is designated the Master and the
other the Slave. The Master ISHSL pin is connected to DGND and
the Slave ISHSL pin is connected to DVDD. The ISHEN pins on
both Master and Slave are connected to DVDD. The SYNC, ISHA,
ISHB, ISHC, ISHREFA, ISHREFB, ISHREFC, ISHCOM and FB pins
are connected from the Master to the Slave and the REF pins are
tied with a 10Ω resistor. Configured this way, the two phase
regulator nearly doubles the load current capacity, limited only by
the Current Share Match tolerance.
The ISL70002SEH ICs operate 180° out-of-phase to minimize
the input ripple current, effectively operating as a single IC at
twice the switching frequency. The Master phase uses the falling
edge of the SYNC clock to initiate the Master switching cycle with
the non-overlap period before the rising edge of LX, while the
Slave phase internally inverts the SYNC input and uses the falling
edge of the inverted copy to start it’s switching cycle. This is
independent of whether the Master phase is configured for an
external clock (Master M/S = DGND) or its internal clock (Master
M/S = DVDD). The Master Error Amplifier and Compensation
controls the two phase regulator while the Slave Error Amplifier is
disabled. The schematic in Figure 3 shows the complete
connections for the Master and Slave.
Operation Initialization
The ISL70002SEH initializes based on the state of the power-on
reset (POR) monitor of the PVINx inputs and the state of the EN
input. Successful initialization prompts a soft-start interval and
the regulator begins slowly ramping the output voltage. Once the
commanded output voltage is within the proper window of
operation, the power-good signal changes state from low to high
indicating proper regulator operation.
Power-On Reset
The POR circuitry prevents the controller from attempting to soft-
start before sufficient bias is present at the PVINx pins.
The POR threshold of the PVINx pins is controlled by the PORSEL
pin. For a nominal 5V supply voltage, PORSEL should be
connected to DVDD. For a nominal 3.3V supply voltage, PORSEL
should be connected to DGND. For nominal supply voltages
between 5V and 3.3V, PORSEL should be connected to DGND.
The POR rising and falling thresholds are shown in the “Electrical
Specifications” table on page 9.
Hysteresis between the rising and falling thresholds insures that
small perturbations on PVINx seen during turn-on/turn-off of the
regulator do not cause inadvertent turn-off/turn-on of the
regulator. When the PVINx pins are below the POR rising
threshold, the internal synchronous power MOSFET switches are
turned off and the LXx pins are held in a high-impedance state.
Enable and Disable
After the POR input requirement is met, the ISL70002SEH
remains in shutdown until the voltage at the enable input rises
above the enable threshold. As shown in Figure 14, the enable
circuit features a comparator type input. In addition to simple
logic on/off control, the enable circuit allows the level of an
external voltage to precisely gate the turn-on/turn-off of the
regulator. An internal I_EN current sink with a typical value of
11µA is only active when the voltage on the EN pin is below the
enable threshold. The current sink pulls the EN pin low. As
V_CONTROL rises, the enable level is not set exclusively by the
resistor divider from V_CONTROL. With the current sink active, the
enable level is defined by Equation 4. R1 is the resistor from the
EN pin to V_CONTROL and R2 is the resistor from the EN pin to the
AGND pin.
V_ENABLE = V_REF ⋅
1
+
R_-----1_--
R2
+ I_EN ⋅ R1
(EQ. 4)
Once the voltage at the EN pin reaches the enable threshold, the
I_EN current sink turns off.
With the part enabled and the I_EN current sink off, the disable
level is set by the resistor divider. The disable level is defined by
Equation 5.
V_DISABLE = V_REF ⋅
1
+
R_-----1_--
R2
(EQ. 5)
The difference between the enable and disable levels provides
adjustable hysteresis so that noise on V_CONTROL does not
interfere with the enabling or disabling of the regulator.
The EN pin should be bypassed to the AGND pin with a 10nF
ceramic capacitor to mitigate SEE.
V_REF = 0.6V
I_EN = 11µA
C_EN = 10nF
V_IN
PVINx
POR
LOGIC
ENABLE
COMPARATOR
+
V_REF
-
V_CONTROL
R1
EN
C_{EN R2}
I_EN
FIGURE 14. ENABLE CIRCUIT
15
FN8264.1
April 5, 2012