ISL70002SEH Datasheet, PDF (4/23 Pages) Intersil Corporation – Rad Hard and SEE Hard 12A Synchronous Buck Regulator with Multi-Phase Current Sharing

ISL70002SEH
Pin Descriptions (Continued)
PIN NUMBER
3, 5, 7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
PIN NAME
DESCRIPTION
ISHREFA/B/C
If configured as a current share Master (ISHSL = DGND, ISHEN = DVDD), the ISHREFA/B/C pins provide a
reference output current equal to 100uA each. If configured as a current share Slave (ISHSL = DVDD,
ISHEN = DVDD), the ISHREFA/B/C pins accept a reference input current. For a current share Slave, this input
current is used together with the ISHA/B/C current to determine the Master’s redundant A/B/C error amp
output current. If using current share, tie ISHREFA/B/C of the MASTER to ISHREFA/B/C of the Slave. If not using
current share, tie ISHREFA/B/C to DVDD. The purpose of the reference current is to reduce the impact of
external noise coupling onto ISHA/B/C. ISHREFA/B/C are tri-stated prior to a valid POR
and when ISHEN = DGND.
AVDD
This pin is the bias supply input to the internal analog control circuitry. Locally filter this pin to AGND using a 1Ω
resistor and a 1µF ceramic capacitor. Locate both filter components as close as possible to the IC. AVDD should
be the same voltage as DVDD and PVINx (±200mV).
AGND
This pin is the analog ground associated with the internal analog control circuitry. Connect this pin directly to
the PCB ground plane.
DGND
This pin is the digital ground associated with the internal digital control circuitry. Connect this pin directly to the
PCB ground plane.
DVDD
This pin is the bias supply input to the internal digital control circuitry. Locally filter this pin to DGND using a 1Ω
resistor and a 1µF ceramic capacitor. Locate both filter components as close as possible to the IC. DVDD should
be the same voltage as AVDD and PVINx (±200mV).
SS
PGOOD
This pin is the soft-start input. Connect a ceramic capacitor from this pin to DGND to set the soft-start output
ramp time in accordance with Equation 2:
t_SS = C_SS ⋅ V_REF ⁄ I_SS
(EQ. 2)
Where:
t_SS = Soft-start output ramp time
C_SS = Soft-start capacitor
V_REF = Reference voltage (0.6V typical)
I_SS = Soft-start charging current (23µA typical)
Soft-start time is adjustable from approximately 2ms to 200ms.
The range of the soft-start capacitor should be 82nF to 8.2µF, inclusive.
If using current share, C_SS of the Slave should be at least twice the C_SS of the Master.
This pin is the power-good output. This pin is an open drain logic output that is pulled to DGND when the output
voltage is outside a ±11% typical regulation window. This pin can be pulled up to any voltage from 0V to 5.5V,
independent of the supply voltage. A nominal 1kΩ to 10kΩ pull-up resistor is recommended. Bypass this pin
to DGND with a 10nF ceramic capacitor to mitigate SEE. If using current share, tie PGOOD of the Master to
PGOOD of the Slave.
ISHCOM
ISHCOM is a bidirectional communication line between a current share Master and a current share Slave. If
using current share, tie ISHCOM of the Master to ISHCOM of the Slave. The Master enables the Slave by
resistively (~ 8.5kΩ) pulling ISHCOM high. The Slave indicates an over-current fault condition to the Master by
pulling ISHCOM low. To mitigate SET, connect a 47pF ceramic capacitor from ISHCOM to the PCB ground plane.
If not using current share this pin should be floated or connected to the PCB ground plane. ISHCOM is tri-stated
if ISHEN is low.
ISHSL
This pin is a logic input that is used to configure the IC as a current share Master or Slave. Tie this pin to DVDD
to configure the IC as a current share Slave. Tie this pin to the PCB ground plane to configure the IC as a current
share Master, or if the current share feature is not being used.
ISHEN
This pin is an input that enables/disables the current share feature. To enable the current share feature, tie this
pin to DVDD. To disable the current share feature, tie this pin to the PCB ground plane.
PORSEL
This pin is the input for selecting the rising and falling POR (Power-On-Reset) thresholds. For a nominal 5V
supply, connect this pin to DVDD. For a nominal 3.3V supply, connect this pin to DGND. For nominal supply
voltages between 5V and 3.3V, connect this pin to DGND.
TDO
This pin is the test data output of the internal BIT circuitry. Connect this pin to the PCB ground plane.
TDI
This pin is the test data input of the internal BIT circuitry. Connect this pin to the PCB ground plane.
TPGM
This pin is a trim input and is used to adjust various internal circuitry. Connect this pin to the PCB ground plane.
GND
This pin is connected to an internal metal die trace that serves as a sensitive node noise shield. Connect this
pin to the PCB ground plane.
4
FN8264.1
April 5, 2012