ISL70002SEH Datasheet, PDF (16/23 Pages) Intersil Corporation – Rad Hard and SEE Hard 12A Synchronous Buck Regulator with Multi-Phase Current Sharing

ISL70002SEH
Soft-Start
Once the POR and enable circuits are satisfied, the regulator
initiates a soft-start. Figure 15 shows that the soft-start circuit
clamps the error amplifier reference voltage to the voltage on an
external soft-start capacitor connected to the SS pin. The
soft-start capacitor is charged by an internal I_SS current source
(23µA typical). As the soft-start capacitor is charged, the output
voltage slowly ramps to the set point determined by the
reference voltage and the feedback network. Once the voltage on
the SS pin is equal to the internal reference voltage (600mV), the
soft-start interval is complete though the SS pin voltage
continues to rise to approximately 1.4V. PGOOD is ENABLED after
SS reached to 1.4V. The controlled ramp of the output voltage
reduces the inrush current during start-up. The soft-start output
ramp interval is defined in Equation 6 and is adjustable from
approximately 2ms to 200ms. The value of the soft-start
capacitor, C_SS, should range from 82nF to 8.2µF, inclusive. The
peak inrush current can be computed from Equation 7. The
soft-start interval should be selected long enough to insure that
the peak in-rush current plus the peak output load current does
not exceed the SS overcurrent trip level of the regulator.
t_SS
=
C_S
S
⋅
V_{-----R----E----F-}
I_SS
(EQ. 6)
I_INRUSH
=
C_OUT
⋅
V_{-----O----U----T--}
t_SS
(EQ. 7)
The soft-start capacitor is immediately discharged by a 2.2Ω
resistor whenever POR conditions are not met or EN is pulled low.
The soft-start discharge time is equal to 256 clock cycles.
V_REF = 0.6V
I_SS = 23µA
R_D = 2.2Ω
PWM
LOGIC
V_OUT
R_T
FB
ERROR
AMPLIFIER
-
+
+
V_{REF RD}
SS
REF
I_SS
R_B
C_SS
C_REF
rises with an external pull-up resistor. The power-good signal
transitions low immediately when the EN pin is pulled low.
The power-good circuitry monitors the FB pin and compares it to
the rising and falling thresholds shown in the “Electrical
Specifications” table on page 10. If the feedback voltage exceeds
the typical rising limit of 111% of the reference voltage, the
PGOOD pin pulls low. The PGOOD pin continues to pull low until
the feedback voltage falls to a typical of 107.5% of the reference
voltage. If the feedback voltage drops below a typical of 89% of
the reference voltage, the PGOOD pin pulls low. The PGOOD pin
continues to pull low until the feedback voltage rises to a typical
92.5% of the reference voltage. The PGOOD pin then releases
and signals the return of the output voltage within the power-
good window.
The PGOOD pin can be pulled up to any voltage from 0V to 5.5V,
independent of the supply voltage. The pull-up resistor should
have a nominal value from 1kΩ to 10kΩ. The PGOOD pin should
be bypassed to DGND with a 10nF ceramic capacitor to mitigate
SEE.
Slope Compensation
The SC0 and SC1 pins select four levels of Current Mode Slope
Compensation. In Current Mode buck regulators, when the duty
cycle approaches and exceeds 50% the regulator will operate in
sub-harmonic oscillation without Slope Compensation. Slope
Compensation is widely considered unnecessary if the duty cycle
is held below 40% and provides better phase margin. Transient
duty cycles must be taken into consideration when selecting the
level of Slope Compensation. The following table describes the
amount of effective current that is added the output powerstage
signal that is used in the PWM modulator.
FSEL
DGND
DGND
DGND
DGND
DVDD
DVDD
DVDD
DVDD
TABLE 1.
SC1
DGND
DGND
DVDD
DVDD
DGND
DGND
DVDD
DVDD
SC0
DGND
DVDD
DGND
DVDD
DGND
DVDD
DGND
DVDD
SLOPE COMP
(A/µs)
0.8
1.6
3.3
6.6
1.7
3.4
6.7
13.4
FIGURE 15. SOFT-START CIRCUIT
Power-Good
The power-good (PGOOD) pin is an open-drain logic output which
indicates when the output voltage of the regulator is within
regulation limits. The power-good pin pulls low during shutdown
and remains low when the controller is enabled. After a
successful soft-start, the PGOOD pin releases and the voltage
Fault Monitoring and Protection
The ISL70002SEH actively monitors output voltage and current
to detect fault conditions. Fault conditions trigger protective
measures to prevent damage to the regulator and external load
device.
Undervoltage Protection
A hysteretic comparator monitors the FB pin of the regulator. The
feedback voltage is compared to an undervoltage threshold that
is a fixed percentage of the reference voltage. Once the
16
FN8264.1
April 5, 2012