ISL62871 Datasheet, PDF (9/25 Pages) Intersil Corporation – PWM DC/DC Controller With VID Inputs For Portable GPU Core-Voltage Regulator

ISL62871, ISL62872
Electrical Specifications
These specifications apply for T_A = -10°C to +100°C, unless otherwise stated.
All typical specifications T_A = +25°C, VCC = 5V. Parameters with MIN and/or MAX limits are 100% tested at
+25°C, unless otherwise specified. Temperature limits established by characterization and are not production
tested. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNIT
OVP Rising Threshold Voltage
OVP Falling Threshold Voltage
OTP Rising Threshold Temperature
(Note 2)
V_OVRTH
V_OVFTH
T_OTRTH
V_FB = %V_SREF
V_FB = %V_SREF
113 116 120
%
100 102 106
%
-
150
-
°C
OTP Hysteresis (Note 2)
T_OTHYS
NOTE:
2. Limits established by characterization and are not production tested.
-
25
-
°C
ISL62872 Functional Pin Descriptions
LGATE (Pin 1)
Low-side MOSFET gate driver output. Connect to the gate
terminal of the low-side MOSFET of the converter.
PGND (Pin 2)
Return current path for the LGATE MOSFET driver. Connect
to the source of the low-side MOSFET.
GND (Pin 3)
IC ground for bias supply and signal reference.
EN (Pin 4)
Enable input for the IC. Pulling EN above the V_ENTHR rising
threshold voltage initializes the soft-start sequence.
VID1 (Pin 5)
Logic input for setpoint voltage selector. Use in conjunction
with the VID0 pin to select among four setpoint reference
voltages.
VID0 (Pin 6)
Logic input for setpoint voltage selector. Use in conjunction
with the VID1 pin to select among four setpoint reference
voltages. External reference input when enabled by
connecting the SET0 pin to the VCC pin.
SREF (Pin 7)
Soft-start and voltage slew-rate programming capacitor
input. Setpoint reference voltage programming resistor input.
Connects internally to the inverting input of the V_SET voltage
setpoint amplifier. See Figure 8 page 12 for capacitor and
resistor connections.
SET0 (Pin 8)
Voltage set-point programming resistor input. See Figure 8
on page 12 for resistor connection.
SET1 (Pin 9)
Voltage set-point programming resistor input. See Figure 8
on page 12 for resistor connection.
SET2 (Pin 10)
Voltage set-point programming resistor input. See Figure 8
on page 12 for resistor connection.
PGOOD (Pin 11)
Power-good open-drain indicator output. This pin changes to
high impedance when the converter is able to supply
regulated voltage. The pull-down resistance between the
PGOOD pin and the GND pin identifies which protective fault
has shut down the regulator. See Table 3 on page 16.
FB (Pin 12)
Voltage feedback sense input. Connects internally to the
inverting input of the control-loop error amplifier. The
converter is in regulation when the voltage at the FB pin
equals the voltage on the SREF pin. The control loop
compensation network connects between the FB pin and the
converter output. See Figure 13 on page 17.
VO (Pin 13)
Output voltage sense input for the R³ modulator. The VO pin
also serves as the reference input for the overcurrent
detection circuit. See Figure 10 on page 14.
OCSET (Pin 14)
Input for the overcurrent detection circuit. The overcurrent
setpoint programming resistor R_OCSET connects from this
pin to the sense node. See Figure 10 on page 14.
NC (Pin 15)
No internal connection. Pin 15 should be connected to the
GND pin.
PHASE (Pin 16)
Return current path for the UGATE high-side MOSFET
driver. V_IN sense input for the R³ modulator. Inductor current
polarity detector input. Connect to junction of output inductor,
high-side MOSFET, and low-side MOSFET. See Figures 2
and 3 on page 4.
UGATE (Pin 17)
High-side MOSFET gate driver output. Connect to the gate
terminal of the high-side MOSFET of the converter.
9
FN6707.0
August 14, 2008