ISL62871 Datasheet, PDF (19/25 Pages) Intersil Corporation – PWM DC/DC Controller With VID Inputs For Portable GPU Core-Voltage Regulator

ISL62871, ISL62872
.
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
Q_GATE = 100nC
0.4
0.2 _20nC
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
DV_{BOOT_CAP} (V)
FIGURE 15. BOOT CAPACITANCE vs BOOT RIPPLE VOLTAGE
Driver Power Dissipation
Switching power dissipation in the driver is mainly a function
of the switching frequency and total gate charge of the
selected MOSFETs. Calculating the power dissipation in the
driver for a desired application is critical to ensuring safe
operation. Exceeding the maximum allowable power
dissipation level will push the IC beyond the maximum
recommended operating junction temperature of +125°C.
When designing the application, it is recommended that the
following calculation be performed to ensure safe operation
at the desired frequency for the selected MOSFETs. The
power dissipated by the drivers is approximated as
Equation 38:
P = F_sw(1.5V_UQ_U + V_LQ_L) + P_L + P_U
(EQ. 38)
Where:
- F_sw is the switching frequency of the PWM signal
- V_U is the upper gate driver bias supply voltage
- V_L is the lower gate driver bias supply voltage
- Q_U is the charge to be delivered by the upper driver into
the gate of the MOSFET and discrete capacitors
- Q_L is the charge to be delivered by the lower driver into
the gate of the MOSFET and discrete capacitors
- P_L is the quiescent power consumption of the lower
driver
- P_U is the quiescent power consumption of the upper
driver
1000
900
800
700
600
500
Q_U = 100nC
Q_L = 200nC
Q_U = 50nC
Q_L = 100nC
Q_U = 50nC
Q_L= 50nC
Q_U = 20nC
Q_L= 50nC
400
300
200
100
0
0 200 400 600 800 1k 1.2k 1.4k 1.6k 1.8k 2k
FREQUENCY (Hz)
FIGURE 16. POWER DISSIPATION vs FREQUENCY
MOSFET Selection and Considerations
Typically, a MOSFET cannot tolerate even brief excursions
beyond their maximum drain to source voltage rating. The
MOSFETs used in the power stage of the converter should
have a maximum V_DS rating that exceeds the sum of the
upper voltage tolerance of the input power source and the
voltage spike that occurs when the MOSFET switches off.
There are several power MOSFETs readily available that are
optimized for DC/DC converter applications. The preferred
high-side MOSFET emphasizes low switch charge so that
the device spends the least amount of time dissipating
power in the linear region. Unlike the low-side MOSFET
which has the drain-source voltage clamped by its body
diode during turn-off, the high-side MOSFET turns off with
V_IN - V_OUT, plus the spike, across it. The preferred low-side
MOSFET emphasizes low r _DS(ON) when fully saturated to
minimize conduction loss.
For the low-side MOSFET, (LS), the power loss can be
assumed to be conductive only and is written as
Equation 39:
P_{CON_LS} ≈ I_LOAD2 ⋅ r_{DS(ON)_LS} ⋅ (1 – D)
(EQ. 39)
For the high-side MOSFET, (HS), its conduction loss is
written as Equation 40:
P_{CON_HS}
=
I_L
O
A
2
D
⋅
r_D
S
(ON)_H
S
⋅
D
(EQ. 40)
For the high-side MOSFET, its switching loss is written as
Equation 41:
P_{SW_HS}
=
V_{-----I--N-----}⋅_---I_{--V----A----L---L---E----Y-----}⋅_---t_{--O-----N-----}⋅_---F_{----S----W---}
2
+
-^V----^I--^N-----^â‹---^I--^P----^E----^A----^K-----^â‹---^t-^O-----^F----^F----^â‹---^F----^S----^W---
2
(EQ. 41)
19
FN6707.0
August 14, 2008