ISL62871 Datasheet, PDF (13/25 Pages) Intersil Corporation – PWM DC/DC Controller With VID Inputs For Portable GPU Core-Voltage Regulator

ISL62871, ISL62872
External Setpoint Reference
The IC can use an external setpoint reference voltage as an
alternative to VID-selected, resistor-programmed setpoints.
This is accomplished by removing all setpoint programming
resistors, connecting the SET0 pin to the VCC pin, and
feeding the external setpoint reference voltage to the VID0
pin. When SET0 and VCC are tied together, the following
internal reconfigurations take place:
- VID0 pin opens its 500nA pull-down current sink
- Reference source selector switch SW4 moves from INT
position (internal 500mV) to EXT position (VID0 pin)
- VID1 pin is disabled
The converter will now be in regulation when the voltage on
the FB pin equals the voltage on the VID0 pin. As with
resistor-programmed setpoints, the reference voltage range
on the VID0 pin is 500mV to 1.5V. Use Equations 1, 2, and 3
beginning on page 11 should it become necessary to
implement an output voltage-divider network to make the
external setpoint reference voltage compatible with the
500mV to 1.5V constraint.
Soft-Start and Voltage-Step Delay
Circuit Description
When the voltage on the VCC pin has ramped above the
rising power-on reset voltage V_{VCC_THR}, and the voltage on
the EN pin has increased above the rising enable threshold
voltage V_ENTHR, the SREF pin releases its discharge clamp
and enables the reference amplifier V_SET. The soft-start
current I_SS is limited to 20µA and is sourced out of the SREF
pin into the parallel RC network of capacitor C_SOFT and
resistance R_T. The resistance R_T is the sum of all the series
connected R_SET programming resistors and is written as
Equation 17:
R_T = R_SET1 + R_SET2 + …R_SET(n)
(EQ. 17)
The voltage on the SREF pin rises as I_SS charges C_SOFT to
the voltage reference setpoint selected by the state of the
VID inputs at the time the EN pin is asserted. The regulator
controls the PWM such that the voltage on the FB pin tracks
the rising voltage on the SREF pin. Once C_SOFT charges to
the selected setpoint voltage, the I_SS current source comes
out of the 20µA current limit and decays to the static value
set by V_SREF ÷ R_T. The elapsed time from when the EN pin
is asserted to when V_SREF has reached the voltage
reference setpoint is the soft-start delay t_SS which is given
by Equation 18:
t_SS = – (I_SS ⋅ C_SOFT) ⋅ LN(1 – -^V----^S_I--_S-^T---_SA----^R-_â‹---^T_R---^--_T-^U---^P-- )
(EQ. 18)
Where:
- I_SS is the soft-start current source at the 20µA limit
- V_START-UP is the setpoint reference voltage selected by
the state of the VID inputs at the time EN is asserted
- R_T is the sum of the R_SET programming resistors
The end of soft-start is detected by I_SS tapering off when
capacitor C_SOFT charges to the designated V_SET voltage
reference setpoint. The SSOK flag is set, the PGOOD pin
goes high, and the I_SS current source changes over to the
voltage-step current source I_VS which has a current limit of
±100µA. Whenever the VID inputs or the external setpoint
reference, programs a different setpoint reference voltage,
the I_VS current source charges or discharges capacitor
C_SOFT to that new level at ±100µA. Once C_SOFT charges to
the selected setpoint voltage, the I_VS current source comes
out of the 100µA current limit and decays to the static value
set by V_SREF ÷ R_T. The elapsed time to charge C_SOFT to
the new voltage is called the voltage-step delay t_VS and is
given by Equation 19:
t_VS = (I_VS ⋅ C_SOFT) ⋅ LN(1 – ⁽---^V----^N----^E-_I--_V-^W---_S----–-_â‹---_RV----_TO-----^L---^D-----⁾)
(EQ. 19)
Where:
- I_VS is the ±100µA setpoint voltage-step current
- V_NEW is the new setpoint voltage selected by the VID
inputs
- V_OLD is the setpoint voltage that V_NEW is changing
from
- R_T is the sum of the R_SET programming resistors
Component Selection For C_SOFT Capacitor
Choosing the C_SOFT capacitor to meet the requirements of a
particular soft-start delay t_SS is calculated with Equation 20,
which is written as:
C_SOFT
=
-----------------------------–---^t--^S----^S-------------------------------
⎛
⎜
⎝
R_T
⋅
L
N(1
–
-^V----^S_I--_S-^T---_SA----^R-_â‹---^T_R---^--_T-^U---^P-- )_{⎠⎟⎞}
(EQ. 20)
Where:
- t_SS is the soft-start delay
- I_SS is the soft-start current source at the 20µA limit
- V_START-UP is the setpoint reference voltage selected by
the state of the VID inputs at the time EN is asserted
- R_T is the sum of the R_SET programming resistors
Choosing the C_SOFT capacitor to meet the requirements of a
particular voltage-step delay t_VS is calculated with
Equation 21, which is written as:
C_SOFT
=
----------------------------------–---^t--^V----^S----------------------------------
⎛
⎜
⎝
R_T
⋅
L N(1
–
-^V----^N---_±-^E--_I--^WV----_S--–---_â‹--^V-_R---^O-_T----^L---^D--)_{⎠⎟⎞}
(EQ. 21)
13
FN6707.0
August 14, 2008