ISL62871 Datasheet, PDF (20/25 Pages) Intersil Corporation – PWM DC/DC Controller With VID Inputs For Portable GPU Core-Voltage Regulator

ISL62871, ISL62872
Where:
- I_VALLEY is the difference of the DC component of the
inductor current minus 1/2 of the inductor ripple current
- I_PEAK is the sum of the DC component of the inductor
current plus 1/2 of the inductor ripple current
- t_ON is the time required to drive the device into
saturation
- t_OFF is the time required to drive the device into cut-off
Layout Considerations
The IC, analog signals, and logic signals should all be on the
same side of the PCB, located away from powerful emission
sources. The power conversion components should be
arranged in a manner similar to the example in Figure 17
where the area enclosed by the current circulating through
the input capacitors, high-side MOSFETs, and low-side
MOSFETs is as small as possible and all located on the
same side of the PCB. The power components can be
located on either side of the PCB relative to the IC.
GND
++
OUTPUT
CAPACITORS
VOUT
PHASE
NODE
HIGH-SIDE
MOSFETS
VIN
LOW-SIDE
MOSFETS
INPUT
CAPACITORS
FIGURE 17. TYPICAL POWER COMPONENT PLACEMENT
Signal Ground
The GND pin is the signal-common also known as analog
ground of the IC. When laying out the PCB, it is very
important that the connection of the GND pin to the bottom
setpoint-reference programming-resistor, bottom feedback
voltage-divider resistor (if used), and the CSOFT capacitor
be made as close as possible to the GND pin on a conductor
not shared by any other components.
In addition to the critical single point connection discussed in
the previous paragraph, the ground plane layer of the PCB
should have a single-point-connected island located under
the area encompassing the IC, setpoint reference
programming components, feedback voltage divider
components, compensation components, CSOFT capacitor,
and the interconnecting traces among the components and
the IC. The island should be connected using several filled
vias to the rest of the ground plane layer at one point that is
not in the path of either large static currents or high di/dt
currents. The single connection point should also be where
the VCC decoupling capacitor and the GND pin of the IC are
connected.
Power Ground
Anywhere not within the analog-ground island is Power
Ground.
VCC and PVCC Pins
Place the decoupling capacitors as close as practical to the
IC. In particular, the PVCC decoupling capacitor should have
a very short and wide connection to the PGND pin. The VCC
decoupling capacitor should not share any vias with the
PVCC decoupling capacitor.
EN, PGOOD, VID0, and VID1 Pins
These are logic signals that are referenced to the GND pin.
Treat as a typical logic signal.
OCSET and VO Pins
The current-sensing network consisting of R_OCSET, R_O, and
C_SEN needs to be connected to the inductor pads for
accurate measurement of the DCR voltage drop. These
components however, should be located physically close to
the OCSET and VO pins with traces leading back to the
inductor. It is critical that the traces are shielded by the
ground plane layer all the way to the inductor pads. The
procedure is the same for resistive current sense.
FB, SREF, SET0, SET1, and SET2 Pins
The input impedance of these pins is high, making it critical
to place the loop compensation components, setpoint
reference programming resistors, feedback voltage divider
resistors, and CSOFT close to the IC, keeping the length of
the traces short.
LGATE, PGND, UGATE, BOOT, and PHASE Pins
The signals going through these traces are high dv/dt and
high di/dt, with high peak charging and discharging current.
The PGND pin can only flow current from the gate-source
charge of the low-side MOSFETs when LGATE goes low.
Ideally, route the trace from the LGATE pin in parallel with
the trace from the PGND pin, route the trace from the
UGATE pin in parallel with the trace from the PHASE pin,
and route the trace from the BOOT pin in parallel with the
trace from the PHASE pin. These pairs of traces should be
short, wide, and away from other traces with high input
impedance; weak signal traces should not be in proximity
with these traces on any layer.
Copper Size for the Phase Node
The parasitic capacitance and parasitic inductance of the
phase node should be kept very low to minimize ringing. It is
best to limit the size of the PHASE node copper in strict
accordance with the current and thermal management of the
application. An MLCC should be connected directly across
the drain of the upper MOSFET and the source of the lower
MOSFET to suppress the turn-off voltage spike.
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FN6707.0
August 14, 2008