ISL62871 Datasheet, PDF (16/25 Pages) Intersil Corporation – PWM DC/DC Controller With VID Inputs For Portable GPU Core-Voltage Regulator

ISL62871, ISL62872
makes this an unattractive option for all but the lowest
current applications. Efficiency is dramatically improved
when the free-wheeling diode is replaced with a MOSFET
that is turned on whenever the high-side MOSFET is turned
off. This modification to the standard DC/DC buck regulator
is referred to as synchronous rectification, the topology
implemented by the ISL62871 and ISL62872 controllers.
Diode Emulation
The polarity of the output inductor current is defined as
positive when conducting away from the phase node, and
defined as negative when conducting towards the phase
node. The DC component of the inductor current is positive,
but the AC component known as the ripple current, can be
either positive or negative. Should the sum of the AC and
DC components of the inductor current remain positive for
the entire switching period, the converter is in
continuous-conduction-mode (CCM.) However, if the
inductor current becomes negative or zero, the converter is
in discontinuous-conduction-mode (DCM.)
Unlike the standard DC/DC buck regulator, the synchronous
rectifier can sink current from the output filter inductor during
DCM, reducing the light-load efficiency with unnecessary
conduction loss as the low-side MOSFET sinks the inductor
current. The ISL62871 and ISL62872 controllers avoid the
DCM conduction loss by making the low-side MOSFET
emulate the current-blocking behavior of a diode. This
smart-diode operation called diode-emulation-mode (DEM)
is triggered when the negative inductor current produces a
positive voltage drop across the r_DS(ON) of the low-side
MOSFET for eight consecutive PWM cycles while the
LGATE pin is high. The converter will exit DEM on the next
PWM pulse after detecting a negative voltage across the
r_DS(ON) of the low-side MOSFET.
It is characteristic of the R³ architecture for the PWM
switching frequency to decrease while in DCM, increasing
efficiency by reducing unnecessary gate-driver switching
losses. The extent of the frequency reduction is proportional
to the reduction of load current. Upon entering DEM, the
PWM frequency is forced to fall approximately 30% by
forcing a similar increase of the window voltage V_W. This
measure is taken to prevent oscillating between modes at
the boundary between CCM and DCM. The 30% increase of
V_W is removed upon exit of DEM, forcing the PWM switching
frequency to jump back to the nominal CCM value.
Power-On Reset
The IC is disabled until the voltage at the VCC pin has
increased above the rising power-on reset (POR) threshold
voltage V_{VCC_THR}. The controller will become disabled
when the voltage at the VCC pin decreases below the falling
POR threshold voltage V_{VCC_THF}. The POR detector has a
noise filter of approximately 1µs.
V_IN and PVCC Voltage Sequence
Prior to pulling EN above the V_ENTHR rising threshold
voltage, the following criteria must be met:
- V_PVCC is at least equivalent to the VCC rising power-on
reset voltage V_{VCC_THR}
- V_VIN must be 3.3V or the minimum required by the
application
Start-Up Timing
Once VCC has ramped above V_{VCC_THR}, the controller can
be enabled by pulling the EN pin voltage above the
input-high threshold V_ENTHR. Approximately 20µs later, the
voltage at the SREF pin begins slewing to the designated
VID set-point. The converter output voltage at the FB
feedback pin follows the voltage at the SREF pin. During
soft-start, The regulator always operates in CCM until the
soft-start sequence is complete.
PGOOD Monitor
The PGOOD pin indicates when the converter is capable of
supplying regulated voltage. The PGOOD pin is an
undefined impedance if the VCC pin has not reached the
rising POR threshold V_{VCC_THR}, or if the VCC pin is below
the falling POR threshold V_{VCC_THF}. The PGOOD
pull-down resistance corresponds to a specific protective
fault, thereby reducing troubleshooting time and effort.
Table 3 maps the pull-down resistance of the PGOOD pin to
the corresponding fault status of the controller.
TABLE 3. PGOOD PULL-DOWN RESISTANCE
CONDITION
PGOOD RESISTANCE
VCC Below POR
Undefined
Soft-Start or Undervoltage
95Ω
Overvoltage
65Ω
Overcurrent
35Ω
LGATE and UGATE MOSFET Gate-Drivers
The LGATE pin and UGATE pins are MOSFET driver
outputs. The LGATE pin drives the low-side MOSFET of the
converter while the UGATE pin drives the high-side
MOSFET of the converter.
The LGATE driver is optimized for low duty-cycle
applications where the low-side MOSFET experiences long
conduction times. In this environment, the low-side
MOSFETs require exceptionally low r_DS(ON) and tend to
have large parasitic charges that conduct transient currents
within the devices in response to high dv/dt switching
present at the phase node. The drain-gate charge in
particular can conduct sufficient current through the driver
pull-down resistance that the V_GS(th) of the device can be
exceeded and turned on. For this reason the LGATE driver
has been designed with low pull-down resistance and high
sink current capability to ensure clamping the MOSFETs
gate voltage below V_GS(th).
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FN6707.0
August 14, 2008