ISL62871 Datasheet, PDF (18/25 Pages) Intersil Corporation – PWM DC/DC Controller With VID Inputs For Portable GPU Core-Voltage Regulator

ISL62871, ISL62872
destruction of circuit components, as well as nuisance OCP
faults.
A DC/DC buck regulator must have output capacitance C_O
into which ripple current I_P-P can flow. Current I_P-P develops
a corresponding ripple voltage V_P-P across C_O, which is the
sum of the voltage drop across the capacitor ESR and of the
voltage change stemming from charge moved in and out of
the capacitor. These two voltages are expressed in
Equations 33 and 34:
ΔV_ESR = I_P-P ⋅ ESR
(EQ. 33)
ΔΔV_C
=
------------^I--^P---^---^P--------------
8 ⋅ C_O ⋅ F_SW
(EQ. 34)
If the output of the converter has to support a load with high
pulsating current, several capacitors will need to be paralleled
to reduce the total ESR until the required V_P-P is achieved.
The inductance of the capacitor can cause a brief voltage dip
if the load transient has an extremely high slew rate. Low
inductance capacitors should be considered. A capacitor
dissipates heat as a function of RMS current and frequency.
Be sure that I_P-P is shared by a sufficient quantity of paralleled
capacitors so that they operate below the maximum rated
RMS current at F_SW. Take into account that the rated value of
a capacitor can fade as much as 50% as the DC voltage
across it increases.
Selection of the Input Capacitor
The important parameters for the bulk input capacitance are
the voltage rating and the RMS current rating. For reliable
operation, select bulk capacitors with voltage and current
ratings above the maximum input voltage and capable of
supplying the RMS current required by the switching circuit.
Their voltage rating should be at least 1.25x greater than the
maximum input voltage, while a voltage rating of 1.5x is a
preferred rating. Figure 14 is a graph of the input RMS ripple
current, normalized relative to output load current, as a
function of duty cycle that is adjusted for converter efficiency.
The ripple current calculation is written as Equation 35:
(
I_MAX2
⋅
(D
–
D²))
+
⎛
⎝
x
⋅
I_MAX2
⋅₁--^D--₂--
⎞
⎠
I_{IN_RMS}
=
----------------------------------------------------------------------------------------------------
I_MAX
(EQ. 35)
Where:
- I_MAX is the maximum continuous I_LOAD of the converter
- x is a multiplier (0 to 1) corresponding to the inductor
peak-to-peak ripple amplitude expressed as a
percentage of I_MAX (0% to 100%)
- D is the duty cycle that is adjusted to take into account
the efficiency of the converter
Duty cycle is written as Equation 36:
D
=
----------^V----^O------------
V_IN ⋅ EFF
(EQ. 36)
In addition to the bulk capacitance, some low ESL ceramic
capacitance is recommended to decouple between the drain
of the high-side MOSFET and the source of the low-side
MOSFET.
0.60
0.55
x=1
0.50
0.45
x = 0.75
0.40
0.35
x = 0.25
x = 0.50
0.30
0.25
0.20
x=0
0.15
0.10
0.05
00 _{0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0}
DUTY CYCLE
FIGURE 14. NORMALIZED RMS INPUT CURRENT FOR x = 0.8
Selecting The Bootstrap Capacitor
Adding an external capacitor across the BOOT and PHASE
pins completes the bootstrap circuit. We selected the
bootstrap capacitor breakdown voltage to be at least 10V.
Although the theoretical maximum voltage of the capacitor is
PVCC-V_DIODE (voltage drop across the boot diode), large
excursions below ground by the phase node requires we
select a capacitor with at least a breakdown rating of 10V. The
bootstrap capacitor can be chosen from Equation 37:
C_BOOT ≥ _Δ---^Q--_V--^G--_B---^A-_O---^T-_O--^E---_T-
(EQ. 37)
Where:
- Q_GATE is the amount of gate charge required to fully
charge the gate of the upper MOSFET
- ΔV_BOOT is the maximum decay across the BOOT
capacitor
As an example, suppose an upper MOSFET has a gate
charge, Q_GATE, of 25nC at 5V and also assume the droop in
the drive voltage over a PWM cycle is 200mV. One will find that
a bootstrap capacitance of at least 0.125µF is required. The
next larger standard value capacitance is 0.15µF. A good
quality ceramic capacitor such as X7R or X5R is
recommended.
18
FN6707.0
August 14, 2008