ISL6263 Datasheet, PDF (9/19 Pages) Intersil Corporation – 5-Bit VID Single-Phase Voltage Regulator for IMVP-6+ Santa Rosa GPU Core

ISL6263
BOOT (Pin 17) - Input power supply for the high-side
MOSFET gate driver. Connect an MLCC bootstrap capacitor
from the BOOT pin to the PHASE pin.
UGATE (Pin 18) - High-side MOSFET gate driver output.
Connect to the gate of the high-side MOSFET.
PHASE (Pin 19) - Current return path for the UGATE high-
side MOSFET gate driver. Detects the polarity of the PHASE
node voltage for diode emulation. Connect the PHASE pin to
the drains of the low-side MOSFETs.
PGND (Pin 20) - Current return path for the LGATE low-side
MOSFET gate driver. The PGND pin only conducts current
when LGATE pulls down. Connect the PGND pin to the
sources of the low-side MOSFETs.
LGATE (Pin 21) - Low-side MOSFET gate driver output.
Connect to the gate of the low-side MOSFET.
PVCC (Pin 22) - Input power supply for the low-side
MOSFET gate driver, and the high-side MOSFET gate
driver, via the internal bootstrap diode connected between
the PVCC and BOOT pins. Connect to +5VDC and decouple
with at least 1µF of an MLCC capacitor from the PVCC pin to
the PGND pin.
VID0:VID4 (Pin 23:Pin 27) - Voltage identification inputs.
VID0 input is the least significant bit (LSB) and VID4 input is
the most significant bit (MSB).
I2UA (Pin 28) - Output of an internal 2µA current source.
Connect a 20kΩ resistor from the I2UA pin to the VSS pin.
VR_ON (Pin 29) - A high logic signal on this pin enables the
converter and a low logic signal disables the converter.
AF_EN (Pin 30) - A high logic signal on this pin enables the
audible frequency filter. A low logic signal on this pin
disables the audible frequency filter and improves the
converter efficiency.
PGOOD (Pin 31) - The PGOOD pin is an open-drain output
that indicates when the converter is able to supply regulated
voltage. Connect the PGOOD pin to a maximum of 5V
through a pull-up resistor.
FDE (Pin 32) - A low logic state on this pin confines the
availability of diode emulation mode to Render Suspend VID
states only. A high logic state on this pin enables diode
emulation for all VID states.
TABLE 1. FDE AND AF_EN STATE TABLE
RENDER
MODE
FDE
0
AF_EN
0
PWM
MODE
CCM
Δ V_W
x
AUDIO
FILTER
x
1
0
CCM/DCM
x
x
0
1
CCM
x
x
1
1
CCM/DCM
x
x
0
0
CCM/DCM +33%
Off
1
0
CCM/DCM +33%
Off
0
1
CCM/DCM None
On
1
1
CCM/DCM None
Off
TABLE 2. VID TABLE FOR INTEL IMVP-6+ V_CCGFX
CORE
V_CCGFX
VID4 VID3 VID2 VID1 VID0
(V)
x
x
x
x
x
0
0
0
0
0
0
1.28750
0
0
0
0
1
1.26175
0
0
0
1
0
1.23600
0
0
0
1
1
1.21025
0
0
1
0
0
1.18450
0
0
1
0
1
1.15875
0
0
1
1
0
1.13300
0
0
1
1
1
1.10725
0
1
0
0
0
1.08150
0
1
0
0
1
1.05575
0
1
0
1
0
1.03000
0
1
0
1
1
1.00425
0
1
1
0
0
0.97850
0
1
1
0
1
0.95275
0
1
1
1
0
0.92700
0
1
1
1
1
0.90125
1
0
0
0
0
0.87550
1
0
0
0
1
0.84975
9
FN9213.2
June 10, 2010