ISL6263 Datasheet, PDF (12/19 Pages) Intersil Corporation – 5-Bit VID Single-Phase Voltage Regulator for IMVP-6+ Santa Rosa GPU Core

ISL6263
frequency further improves efficiency by reducing switching
losses. The converter will automatically enter DEM after
eight consecutive PWM pulses where the PHASE pin has
detected positive voltage shortly after the LGATE pin has
gone high. The converter will return to CCM on the following
cycle after the PHASE pin detects negative voltage shortly
after the LGATE pin has gone high, indicating that the body
diode of the low-side MOSFET is conducting positive
inductor current. The converter inhibits the automatic 33%
change of V_W whenever the audio filter is enabled.
Smooth mode transitions are facilitated by the R³ modulator
which correctly maintains the internally synthesized ripple
current information throughout mode transitions.
Protection
The ISL6263 provides overcurrent protection (OCP),
overvoltage protection (OVP), and undervoltage protection
(UVP) as shown in Table 3.
Overcurrent protection is tied to the voltage droop, which is
determined by the resistors selected in the Static Droop
Design Using DCR Sensing section. After the load line is set,
the OCSET resistor can be selected. The OCP threshold
detector is checked every 15µs and will increment a counter
if the OCP threshold is exceeded, conversely the counter will
be decremented if the load current is below the OCP
threshold. The counter will latch an OCP fault when the
counter reaches eight. The fastest OCP response for
overcurrent events occurring above the OCP threshold but
below twice the OCP threshold is 120µs, which is eight
counts at 15µs each. The ISL6263 will latch an OCP fault
within 2µs for an overcurrent exceeding twice the OCP
threshold to maximize protection against hard shorts. The
value of R_OCSET is calculated as Equation 1:
R_OCSET
=
-^I-^O-----^C-----^â‹---^R-----^d---^r--^o----^o---^p-
10 μ A
(EQ. 1)
For example: The desired overcurrent trip level, I_oc, is 30A,
R_droop load-line is 8mΩ, Equation 1 gives R_OCSET = 24kΩ.
Undervoltage protection is independent of the overcurrent
protection. If the output voltage measured on the VO pin is
less than +300mV below the voltage on the SOFT pin for
longer than 1ms, the controller will latch a UVP fault. If the
output voltage measured on the VO pin is greater than
+200mV above the voltage on the SOFT pin for longer than
1ms, the controller will latch an OVP fault. Keep in mind that
V_SOFT will equal the voltage level commanded by the VID
states only after the soft-start capacitor C_SOFT has slewed to
the VID DAC output voltage. The UVP and OVP detection
circuits act on static and dynamic V_SOFT voltage.
When an OCP, OVP, or UVP fault has been latched, PGOOD
becomes a low impedance and the gate driver outputs
UGATE and LGATE are pulled low. The energy stored in the
inductor is dissipated as current flows through the low-side
MOSFET body diode. The controller will remain latched in
the fault state until the VR_ON pin has been pulled below the
falling VR_ON threshold voltage V_{VR_ONL} or until VDD has
gone below the falling POR threshold voltage ^V_{VDD_THF}.
A severe-overvoltage protection fault occurs immediately
after the voltage between the VO and VSS pins exceed the
rising severe-overvoltage threshold V_OVPS which is 1.545V,
the same reference voltage used by the VID DAC. The
ISL6263 will latch UGATE and PGOOD low but unlike other
protective faults, LGATE remains high until the voltage
between VO and VSS falls below approximately 0.77V, at
which time LGATE is pulled low. The LGATE pin will continue
to switch high and low at 1.545V and 0.77V until VDD has
gone below the falling POR threshold voltage ^V_{VDD_THF.}
This provides maximum protection against a shorted high-
side MOSFET while preventing the output voltage from
ringing below ground. The severe-overvoltage fault circuit
can be triggered after another fault has already been
latched.
TABLE 3. FAULT PROTECTION SUMMARY OF ISL6263
FAULT TYPE
FAULT
DURATION
PRIOR TO
PROTECTION
PROTECTION
ACTIONS
FAULT
RESET
Overcurrent
120µs
LGATE, UGATE, and Cycle
PGOOD latched low VR_ON or
VDD
Short Circuit
<2µs
LGATE, UGATE, and Cycle
PGOOD latched low VR_ON or
VDD
Overvoltage
(+200mV)
between VO pin
and SOFT pin
1ms
LGATE, UGATE, and Cycle
PGOOD latched low VR_ON or
VDD
Severe
Overvoltage
(+1.55V)
between VO pin
and VSS pin
Immediately
UGATE, and
Cycle
PGOOD latched low, VDD only
LGATE toggles ON
when VO>1.55V
OFF when
VO <0.77V
until fault reset
Undervoltage
(-300mV)
between VO pin
and SOFT pin
1ms
LGATE, UGATE, and Cycle
PGOOD latched low VR_ON or
VDD
Gate-Driver Outputs LGATE and UGATE
The ISL6263 has internal high-side and low-side N-Channel
MOSFET gate-drivers. The LGATE driver is optimized for
low duty-cycle applications where the low-side MOSFET
conduction losses are dominant. The LGATE pull-down
resistance is very low in order to clamp the gate-source
voltage of the MOSFET below the V_GS(th) at turnoff. The
current transient through the low-side gate at turnoff can be
considerable due to the characteristic large switching charge
of a low r _DS(on) MOSFET.
12
FN9213.2
June 10, 2010