ISL6263 Datasheet, PDF (16/19 Pages) Intersil Corporation – 5-Bit VID Single-Phase Voltage Regulator for IMVP-6+ Santa Rosa GPU Core

ISL6263
To see whether the NTC network successfully compensates
the DCR change over temperature, one can apply full load
current and wait for the thermal steady state and see how
much the output voltage deviates from the initial voltage
reading. A good compensation can limit the drift to less than
2mV. If the output voltage is decreasing when the temperature
increases, that ratio between the NTC thermistor value and
the rest of the resistor divider network has to be increased.
Following the evaluation board value and layout of NTC
placement will minimize the engineering time.
The current sensing traces should be routed directly to the
inductor pads for accurate DCR voltage drop measurement.
However, due to layout imperfection, the calculated R_DRP2
may still need slight adjustment to achieve optimum load line
slope. It is recommended to adjust R_DRP2 after the system
has achieved thermal equilibrium at full load. For example, if
the maximum load current is 20A, one should apply a 20A
load current and look for 160mV output voltage droop. If the
voltage droop is 155mV, the new value of R_DRP2 is
calculated by Equation 16:
R_DRP2new
=
1_----6_---0_----m_-----V_---
155 m V
⋅
(
R_D
R
P
1
–
R_DPR2
)
–
R_D
RP1
(EQ. 16)
For the best accuracy, the effective resistance on the DFB
and VSUM pins should be identical so that the bias current
of the droop amplifier does not cause an offset voltage.
Dynamic Droop Capacitor Design Using DCR
Sensing
Figure 10 shows the desired waveforms during load
transient response. V_CCGFX needs to follow the change in
I_core as close as possible. The transient response of
V_CCGFX is determined by several factors, namely the choice
of output inductor, output capacitor, compensator design,
and the design of droop capacitor C_N.
If C_N is designed correctly, the voltage V_DROOP -V_O will be
an excellent representation of the inductor current. Given the
correct C_N design, V_CCGFX has the best chance of tracking
I_CORE, if not, its voltage will be distorted from the actual
waveform of the inductor current and worsens the transient
response. Figure 11 shows the transient response when C_N
is too small allowing V_CCGFX to sag excessively during the
load transient. Figure 12 shows the transient response when
C_N is too large. V_CCGFX takes too long to droop to its final
value.
16
i_core
ΔI_core
V_core
V_core
ΔV_core
ΔV_core= ΔI_core×R_droop
FIGURE 10. DESIRED LOAD TRANSIENT RESPONSE
WAVEFORMS
i_core
V_core
V_core
FIGURE 11. LOAD TRANSIENT RESPONSE WHEN C_N IS TOO
SMALL
i_core
V_core
V_core
FIGURE 12. LOAD TRANSIENT RESPONSE WHEN C_N IS TOO
LARGE
The current sensing network consists of R_NTCEQ, R_S, and
C_N. The effective resistance is the parallel of R_NTCEQ and
R_S. The RC time constant of the current sensing network
needs to match the L/DCR time constant of the inductor to
get the correct representation of the inductor current
waveform. Equation 17 shows this relationship:
------^L-------
DCR
=
⎛
⎜
⎝
R^-R----_N^-N---_T^-T---_C^-C---_E^-E---_Q^{-Q-----+-⋅---RR----S-}_S^--_{⎠⎟⎞}
⋅ C_N
(EQ. 17)
Solution of C_N yields Equation 18:
⎛
⎝
D^-----C^-L----R^{---⎠⎞}
C_N
=
--------------------------------------------
⎛
⎜
⎝
R^-R----_N^-N---_T^-T---_C^-C---_E^-E---_Q^{-Q-----+-⋅---RR----S-}_S^--_{⎠⎟⎞}
(EQ. 18)
For example: L = 0.45µH, DCR = 1.1mΩ, R_S = 7.68kΩ, and
R_NTCEQ = 3.4kΩ:
⎛
⎝
-⁰¹---^.-_.-⁴¹---⁵-_m---^μ---_Ω-^H--_⎠⎞
C_N
=
------------------------------------------------ =
⎛
⎝
3^-3---.^-.-44^---k^-k---Ω^{-Ω-----+-⋅---7-}7^--.-.^-6-6^--8-8^---k-k^{---ΩΩ--- ⎠⎞}
174 n F
(EQ. 19)
Since the inductance and the DCR typically have 20% and
7% tolerance respectively, C_N needs to be fine tuned on the
FN9213.2
June 10, 2010