ISL6263 Datasheet, PDF (17/19 Pages) Intersil Corporation – 5-Bit VID Single-Phase Voltage Regulator for IMVP-6+ Santa Rosa GPU Core

ISL6263
actual board by examining the transient voltage. It is
recommended to choose the minimum capacitance based
on the maximum inductance. C_N also needs to be a high-
grade capacitor such as NPO/COG or X7R with tight
tolerance. The NPO/COG caps are only available in small
capacitance values. In order to use such capacitors, the
resistors and thermistors surrounding the droop voltage
sensing and droop amplifier need to be scaled up 10x to
reduce the capacitance by 10x.
Static and Dynamic Droop using Discrete Resistor
Sensing
Figure 3 shows a detailed schematic using discrete resistor
sensing of the inductor current. Figure 9 shows the
equivalent circuit. Since the current sensing resistor voltage
represents the actual inductor current information, R_S and
C_N simply provide noise filtering. A low ESL sensing resistor
is strongly recommended for R_SNS because this parameter
is the most significant source of noise that affects discrete
resistor sensing. It is recommended to start out using 100Ω
for R_S and 47pF for C_N. Since the current sensing
resistance changes very little with temperature, the NTC
network is not needed for thermal compensation. Discrete
resistor sensing droop design follows the same approach as
DCR sensing. The voltage on the current sensing resistor is
given by Equation 20:
V_RSNS = I_o ⋅ R_SNS
(EQ. 20)
Equation 21 shows the droop amplifier gain. So the actual
droop is given by:
R_droop
=
R_S
N
S
⋅
⎛
⎜
⎝
1
+
RR_{-----DD----RR----PP----21--⎠⎟⎞}
(EQ. 21)
Solution to R_DRP2 yields Equation 22:
R_DRP2
=
R_DRP1
⋅
⎛
⎜
⎝
R_{-----d---r---o---o---p-}
R_SNS
–
⎞
1⎟
⎠
(EQ. 22)
For example: R_droop = 8.0mΩ, R_SNS = 1.0mΩ, and
R_DRP1 = 1kΩ, R_DRP2 then = 7kΩ.
The current sensing traces should be routed directly to the
current sensing resistor pads for accurate measurement.
However, due to layout imperfection, the calculated R_DRP2
may still need slight adjustment to achieve optimum load line
slope. It is recommended to adjust R_DRP2 after the system
has achieved thermal equilibrium at full load.
Dynamic Mode of Operation - Compensation
Parameters
The voltage regulator is equivalent to a voltage source in
series with the output impedance. The voltage source is the
VID state and the output impedance is 8.0mΩ in order to
achieve the 8.0mV/A load line. It is highly recommended to
design the compensation such that the regulator output
impedance is 8.0mΩ. Intersil provides a spreadsheet to
calculate the compensator parameters. Caution needs to be
used in choosing the input resistor to the FB pin. Excessively
high resistance will cause an error to the output voltage
regulation due to the bias current flowing through the FB pin.
It is recommended to keep this resistor below 3kΩ.
Layout Considerations
As a general rule, power should be on the bottom layer of
the PCB and weak analog or logic signals are on the top
layer of the PCB. The ground-plane layer should be adjacent
to the top layer to provide shielding.
Inductor Current Sensing and the NTC Placement
It is crucial that the inductor current be sensed directly at the
PCB pads of the sense element, be it DCR sensed or
discrete resistor sensed. The effect of the NTC on the
inductor DCR thermal drift is directly proportional to its
thermal coupling with the inductor and thus, the physical
proximity to it.
Signal Ground and Power Ground
The ground plane layer should have a single point
connection to the analog ground at the VSS pin. The VSS
island should be located under the IC package along with
the weak analog traces and components. The paddle on the
bottom of the ISL6263 QFN package is not electrically
connected to the IC however, it is recommended to make a
good thermal connection to the VSS island using several
vias. Connect the input capacitors, the output capacitors,
and the source of the lower MOSFETs to the power ground
plane.
LGATE, PVCC, and PGND
PGND is the return path for the pull-down of the LGATE
low-side MOSFET gate driver. Ideally, PGND should be
connected to the source of the low-side MOSFET with a
low-resistance, low-inductance path. The LGATE trace
should be routed in parallel with the trace from the PGND
pin. These two traces should be short, wide, and away from
other traces because of the high peak current and extremely
fast dv/dt. PVCC should be decoupled to PGND with a
ceramic capacitor physically located as close as practical to
the IC pins.
VIAS TO
GROUND
PLANE
INDUCTOR
HIGH-SIDE
MOSFETS
GND
VOUT
OUTPUT
CAPACITORS
SCHOTTKY
DIODE
PHASE
NODE
LOW-SIDE
MOSFETS
INPUT
VIN
CAPACITORS
FIGURE 13. TYPICAL POWER COMPONENT PLACEMENT
17
FN9213.2
June 10, 2010