ISL6263 Datasheet, PDF (10/19 Pages) Intersil Corporation – 5-Bit VID Single-Phase Voltage Regulator for IMVP-6+ Santa Rosa GPU Core

ISL6263
TABLE 2. VID TABLE FOR INTEL IMVP-6+ V_CCGFX
CORE (Continued)
V_CCGFX
VID4 VID3 VID2 VID1 VID0
(V)
1
0
0
1
0 0.82400V
1
0
0
1
1 0.79825V
1
0
1
0
0 0.77250V
1
0
1
0
1 0.74675V
1
0
1
1
0 0.72100V
1
0
1
1
1 0.69525V
1
1
0
0
0 0.66950V
1
1
0
0
1 0.64375V
1
1
0
1
0 0.61800V
1
1
0
1
1 0.59225V
1
1
1
0
0 0.56650V
1
1
1
0
1 0.54075V
1
1
1
1
0 0.51500V
1
1
1
1
1 0.41200V
Theory of Operation
The R³ Modulator
The heart of the ISL6263 is Intersil’s Robust-Ripple-
Regulator (R³) Technology™. The R³ modulator is a hybrid
of fixed frequency PWM control, and variable frequency
hysteretic control that will simultaneously affect the PWM
switching frequency and PWM duty cycle in response to
input voltage and output load transients.
The term “Ripple” in the name “Robust-Ripple-Regulator”
refers to the synthesized voltage-ripple signal V_R that
appears across the internal ripple-capacitor C_R. The V_R
signal is a representation of the output inductor ripple
current. Transconductance amplifiers measuring the input
voltage of the converter and the output set-point voltage
V_SOFT, together produce the voltage-ripple signal V_R.
A voltage window signal V_W is created across the VW and
COMP pins by sourcing a current proportional to g_mV_soft
through a parallel network consisting of resistor R_FSET and
capacitor C_FSET. The synthesized voltage-ripple signal V_R
along with similar companion signals are converted into
PWM pulses.
The PWM frequency is proportional to the difference in
amplitude between V_W and V_COMP. Operating on these
large-amplitude, low noise synthesized signals allows the
ISL6263 to achieve lower output ripple and lower phase jitter
than either conventional hysteretic or fixed frequency PWM
controllers. Unlike conventional hysteretic converters, the
ISL6263 has an error amplifier that allows the controller to
maintain tight voltage regulation accuracy throughout the
VID range from 0.41200V to 1.28750V.
Power-On Reset
The ISL6263 is disabled until the voltage at the VDD pin has
increased above the rising VDD power-on reset (POR)
V_{DD_THR} threshold voltage. The controller will become
disabled when the voltage at the VDD pin decreases below
the falling POR V_{DD_THF} threshold voltage.
Start-Up Timing
Figure 4 shows the ISL6263 start-up timing. Once VDD has
ramped above V_{DD_THR}, the controller can be enabled by
pulling the VR_ON pin voltage above the input-high
threshold V_{VR_ONH}. Approximately 100µs later, the soft-start
capacitor C_SOFT begins slewing to the designated VID
set-point as it is charged by the soft-start current source I_SS.
The V_CCGFX output voltage of the converter follows the
V_SOFT voltage ramp to within 10% of the VID set-point then
counts 6 switching cycles, then changes the open-drain
output of the PGOOD pin to high impedance. During
soft-start, the regulator always operates in continuous
conduction mode (CCM).
VR_ON
~100µs
V_SOFT/ V_CCGFX
90%
PGOOD
6 SWITCHING CYCLES
FIGURE 4. ISL6263 START-UP TIMING
Static Regulation
The V_CCGFX output voltage will be regulated to the value set
by the VID inputs per Table 2. A true differential amplifier
connected to the VSEN and RTN pins implements processor
socket Kelvin sensing for precise core voltage regulation at
the GPU voltage sense points.
As the load current increases from zero, the V_CCGFX output
voltage will droop from the VID set-point by an amount
proportional to the IMVP-6+ load line. The ISL6263 can
accommodate DCR current sensing or discrete resistor
current sensing. The DCR current sensing uses the intrinsic
series resistance of the output inductor as shown in the
application circuit of Figure 2. The discrete resistor current
sensing uses a shunt connected in series with the output
inductor as shown in the application circuit of Figure 3. In
both cases the signal is fed to the non-inverting input of the
DROOP amplifier at the VSUM pin, where it is measured
differentially with respect to the output voltage of the
converter at the VO pin and amplified. The voltage at the
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FN9213.2
June 10, 2010