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ISL5314 Datasheet, PDF (9/17 Pages) Intersil Corporation – Direct Digital Synthesizer
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ISL5314
Electrical Specifications
AVDD = DVDD = +5V (unless otherwise noted), VREF = Internal 1.2V, IOUTFS = 20mA, TA = -40°C to +85°C for
all Min and Max Values. TA = +25°C for All Typical Values. Boldface limits apply over the operating
temperature range, -40°C to +85°C. (Continued)
PARAMETER
TEST CONDITIONS
MIN
MAX
(Note 4) TYP (Note 4) UNITS
Spurious Free Dynamic Range,
fCLK = 125MSPS, fOUT = 40.4MHz
SFDR to Nyquist (fCLK/2) (Notes 7, 10) fCLK = 125MSPS, fOUT = 10.1MHz
fCLK = 125MSPS, fOUT = 5.02MHz
fCLK = 100MSPS, fOUT = 40.4MHz
fCLK = 100MSPS, fOUT = 20.2MHz
fCLK = 100MSPS, fOUT = 5.04MHz
fCLK = 100MSPS, fOUT = 2.51MHz
fCLK = 50MSPS, fOUT = 20.2MHz
fCLK = 50MSPS, fOUT = 5.02MHz
fCLK = 50MSPS, fOUT = 2.51MHz
fCLK = 50MSPS, fOUT = 1.00MHz
fCLK = 25MSPS, fOUT = 1.0MHz
DAC REFERENCE VOLTAGE
-
40
-
dBc
57
63
-
dBc
-
72
-
dBc
-
40
-
dBc
-
49
-
dBc
-
72
-
dBc
-
73
-
dBc
-
45
-
dBc
-
68
-
dBc
-
72
-
dBc
-
71
-
dBc
-
72
-
dBc
Internal Reference Voltage, VFSADJ
Internal Reference Voltage Drift
Pin 13 Voltage with Internal Reference
1.13
1.2
1.28
V
-
±60
-
ppm/°C
Internal Reference Output Current
Sink/Source Capability
-
±0.1
-
μA
Reference Input Impedance
-
1
-
MΩ
Reference Input Multiplying Bandwidth (Notes 7, 10)
-
1.4
-
MHz
DIGITAL INPUTS
Input Logic High Voltage with
5V Digital Supply, VIH
Input Logic High Voltage with
3V Digital Supply, VIH
Input Logic Low Voltage with
5V Digital Supply, VIL
Input Logic Low Voltage with
3V Digital Supply, VIL
Input Logic Current, IIH
Input Logic Current, IIL
Digital Input Capacitance, CIN
TIMING CHARACTERISTICS
(Note 6)
(Note 6)
(Note 6)
(Note 6)
3.5
5
-
V
2.0
3
-
V
-
0
1.3
V
-
0
0.8
V
-10
-
+10
µA
-10
-
+10
µA
-
4
-
pF
Maximum Clock Rate, fCLK
Maximum Clock Rate, fCLK
CLK Pulse Width, tCW
Maximum Parallel Write Rate
+5V DVDD, +5V AVDD (Note 6)
+3.3V DVDD, +5V AVDD (Note 6)
CLK pin (Note 6)
Rate of WR pin
125
-
100
-
5
-
50
-
-
MSPS
-
MSPS
-
ns
-
MSPS
WR Pulse Width, tWW
Data Setup Time, tDS
Data Hold Time, tDH
(Note 6)
Between DATA and WR (Note 6)
Between DATA and WR (Note 6)
5
-
-
ns
10
-
-
ns
0
-
-
ns
9
FN4901.3
January 19, 2010
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