ISL5314 Datasheet, PDF (8/17 Pages) Intersil Corporation – Direct Digital Synthesizer

ISL5314
Absolute Maximum Ratings
Digital Supply Voltage DV_DD to DGND . . . . . . . . . . . . . . . . . . +5.5V
Analog Supply Voltage AV_DD to AGND . . . . . . . . . . . . . . . . . . +5.5V
Grounds, AGND To DGND . . . . . . . . . . . . . . . . . . . . -0.3V To +0.3V
Digital Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . DV_DD + 0.3V
Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AV_DD + 0.3V
Analog Output Current (I_OUT) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Thermal Information
Thermal Resistance (Typical, Note 3)
θ_JA(°C/W)
LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
3. θ_JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
AV_DD = DV_DD = +5V (unless otherwise noted), V_REF = Internal 1.2V, IOUTFS = 20mA, T_A = -40°C to +85°C for
all Min and Max Values. T_A = +25°C for All Typical Values. Boldface limits apply over the operating
temperature range, -40°C to +85°C.
PARAMETER
TEST CONDITIONS
MIN
MAX
(Note 4) TYP (Note 4) UNITS
DAC CHARACTERISTICS
DAC Resolution
14
-
-
Bits
Integral Linearity Error, INL
“Best Fit” Straight Line (Note 10)
-5
+2.5
+6
LSB
Differential Linearity Error, DNL
(Note 10)
-2
+1.5
+4
LSB
Offset Error, I_OS
Offset Drift Coefficient
(Note 10)
(Note 10)
-0.025
+0.025 % FSR
-
0.1
-
ppm
FSR/°C
Full Scale Gain Error
With Internal Reference (Notes 5, 10)
-10
±1
+10 % FSR
Full Scale Gain Drift
With Internal Reference (Note 10)
-
±50
-
ppm
FSR/°C
Full Scale Output Current
(Note 6)
2
-
20
mA
Output Voltage Compliance Range (Note 6, 10)
-1.0
-
1.25
V
DAC DYNAMIC CHARACTERISTICS
Maximum Clock Rate, f_CLK
Maximum Clock Rate, f_CLK
Output Settling Time, (t_SETT)
Output Rise Time
+5V DV_DD, +5V AV_DD (Note 6)
+3.3V DV_DD, +5V AV_DD (Note 6)
±0.05% (±8 LSB) (Note 10)
Full Scale Step
125
-
100
-
-
35
-
2.5
-
MSPS
-
MSPS
-
ns
-
ns
Output Fall Time
Full Scale Step
-
2.5
-
ns
Output Capacitance
-
25
-
pF
Output Noise
IOUTFS = 20mA
-
50
-
pA/ √Hz
IOUTFS = 2mA
-
30
-
pA/ √Hz
AC CHARACTERISTICS
Spurious Free Dynamic Range,
SFDR Within a Window (Notes 7, 10)
f_CLK = 100MSPS, f_OUT = 20MHz, 5MHz Span
f_CLK = 100MSPS, f_OUT = 5MHz, 8MHz Span
f_CLK = 50MSPS, f_OUT = 5MHz, 8MHz Span
-
93
-
dBc
-
93
-
dBc
-
93
-
dBc
8
FN4901.3
January 19, 2010