ISL5314 Datasheet, PDF (14/17 Pages) Intersil Corporation – Direct Digital Synthesizer

Timing Diagrams (Continued)
ISL5314
ONE CLK RISING EDGE
REQUIRED WHILE RESET LOW
CLK (f_CLK)
RESET
t_RS
t_RL = 11 CLK RISING EDGES
ANALOG OUT
PREVIOUS REGISTER VALUES
FIGURE 5. RESET TIMING AND LATENCY
RESET REGISTER VALUES
CLK (f_CLK)
t_EH
ENOFR
t_ES
ANALOG OUT
CENTER FREQUENCY ONLY
CENTER + OFFSET
CENTER ONLY
CENTER
+ OFFSET
t_EL = 14 CLK RISING EDGES
FIGURE 6. ENOFR (ENABLE OFFSET FREQUENCY REGISTER) TIMING AND LATENCY (RESET = HIGH)
14
FN4901.3
January 19, 2010