ISL5314 Datasheet, PDF (15/17 Pages) Intersil Corporation – Direct Digital Synthesizer

Timing Diagrams (Continued)
RESET
SDATA
t_SDS
t_SDH
ISL5314
t_SDW
SERIAL DATA (8 BITS SHOWN; MAX IS 40)
DON’T CARE
SCLK
SERIAL FREQ ^tSSS
REGISTER
SSYNC
CLK (f_CLK)
SCLK EDGES = SERIAL BITS + 3
t_SSH
OLD FREQ IN THE
SERIAL REGISTER
t_SCW
t_SSW
DON’T CARE (ASSUMED CONTINUOUSLY RUNNING)
DON’T CARE (CAN FREE RUN)
NEW FREQ LOADED
IN THE SERIAL REGISTER
t = 12 f_CLK RISING EDGES
DON’T CARE
ANALOG OUT
OLD FREQ
NEW FREQ
FIGURE 7. SERIAL PROGRAMMING, SYNC EARLY MODE (REPRESENTS MINIMUM SCLKS REQUIRED. SCLK CAN FREE RUN.)
CONTROL REGISTER 12 IS SET TO 0001 00XX.
RESET
SDATA
SERIAL DATA (8 BITS SHOWN; MAX IS 40)
SCLK
SERIAL FREQ
REGISTER
SSYNC
SCLK EDGES = SERIAL BITS + 3
OLD FREQ IN THE
SERIAL REGISTER
CLK (f_CLK)
DON’T CARE (ASSUMED CONTINUOUSLY RUNNING)
DON’T CARE
DON’T CARE (CAN FREE RUN)
NEW FREQ LOADED
IN THE SERIAL REGISTER
t = 12 f_CLK RISING EDGES
DON’T CARE
ANALOG OUT
OLD FREQ
NEW FREQ
FIGURE 8. SERIAL PROGRAMMING, SYNC LATE BURST MODE (REPRESENTS MINIMUM SCLKS REQUIRED; SCLK CAN FREE RUN);
CONTROL REGISTER 12 IS SET TO 0000 00XX.
15
FN4901.3
January 19, 2010