ISL5314 Datasheet, PDF (13/17 Pages) Intersil Corporation – Direct Digital Synthesizer

Timing Diagrams
WE
ADDR
DATA
WRITE
CLK (f_CLK)
UPDATE
ANALOG OUT
ISL5314
t_WS
t_AS
t_AH
A₀
A₁
A₂
t_WH
A_N
DON’T CARE
W₀
W₁
W₂
W_N
t_DS
t_DH
1 WRITE CYCLE FOR EVERY REGISTER
DON’T CARE
DON’T CARE
DON’T CARE
t_US
t_UD
t_UL = 14 CLK RISING EDGES
OLD FREQ
NEW FREQ
FIGURE 3. PARALLEL-LOAD METHOD 1, UPDATE ACTIVE AFTER LOADING REGISTERS (RESET = HIGH)
WE
t_WS
t_WH
t_AS t_AH
ADDR
A₀
A₁
A₂
A_N
DON’T CARE
DATA
WRITE
CLK (f_CLK)
UPDATE
W₀
W₁
W₂
W_N
t_DS
t_DH
1 WRITE CYCLE FOR EVERY REGISTER
DON’T CARE
DON’T CARE
DON’T CARE
t_UL= 11 CLK RISING EDGES
ANALOG OUT
PREVIOUS FREQ
ENTIRE NEW FREQ
PARTIAL UPDATES
FIGURE 4. PARALLEL-LOAD METHOD 2, UPDATE ACTIVE WHILE LOADING REGISTERS (RESET = HIGH)
13
FN4901.3
January 19, 2010