ISL5314 Datasheet, PDF (2/17 Pages) Intersil Corporation – Direct Digital Synthesizer

ISL5314
Pin Descriptions
PIN NO.
44-48, 1-3
PIN NAME
C(7:0)
42
WR
40
35-38
WE
A(3:0)
6
CLK
8
RESET
30
SCLK
27
SDATA
32
SSYNC
9
UPDATE
33, 34
PH(1:0)
4
ENOFR
10
COMPOUT
11
REFLO
12
REFIO
13
FSADJ
14
19
18
17
20
15, 16, 21, 24
7, 26, 31, 43
5, 25, 28, 29, 41
22, 23
39
COMP1
COMP2
IOUTA
IOUTB
AVDD
AGND
DVDD
DGND
IN+, IN-
NC
TYPE
PIN DESCRIPTION
Input 8-bit processor input data bus. C7 is the MSB. Data is written to the control register selected on
A(3:0) on the rising edge of WR when WE is active.
Input Write clock for the processor interface. Parallel data is clocked into the chip on the rising edge of
WR.
Input Write enable. Active low. WE must be active when writing data to the chip.
Input Processor interface address bus. These pins select the destination register for data on the C(7:0)
bus. A3 is the MSB.
Clock NCO and DAC clock. The phase accumulator and DAC output update on the rising edge of this
clock. CLK can be asynchronous to the WR clock.
Input Reset. Active low. Resets control registers to their default states (see register description table)
and zeroes the feedback in the phase accumulator. UPDATE must be low for Reset to occur.
Input Serial clock. Polarity is programmable. See control word 12. May be asynchronous to CLK. If not
used, connect to DGND.
Input Serial data. See control word 12. If not used, connect to DGND.
Input Serial sync. See control word 12. If not used, connect to DGND.
Input Active low. Updates the active control registers only. It has no effect on the ENOFR or PH(1:0)
pins. This pin is provided for updating an entire frequency word at once rather than byte by byte.
Input
Phase offset bits. The phase of the output is shifted. If not used, these pins should be grounded.
00 – 0° reference
01 – 90° shift
10 – 180° shift
11 – 270° shift
Input
Enable offset frequency. Active high. When high, the offset frequency bus is enabled to the phase
accumulator. When low, the offset frequency bus is zeroed. This pin does not affect the contents
of the offset frequency registers. If not used, the pin should be grounded.
Output Comparator output.
Input Connect to analog ground to enable the DAC’s internal 1.2V reference or connect to AV_DD to
disable the internal reference.
Input Reference voltage input for the DAC if internal reference is disabled. Recommend the use of a
0.1µF cap to ground from the REFIO pin when a DC reference voltage is used.
Full scale current adjust for the DAC. Use a resistor to ground (R_SET) to adjust the full scale
output current. Full Scale Output Current = 32 x V_FSADJ/R_SET, where V_FSADJ equals the
reference voltage.
Noise reduction for the DAC. Connect a 0.1µF cap to AV_DD plane.
Noise reduction for the DAC. Connect a 0.1µF cap to AGND plane.
Output DAC current output.
Output DAC complementary current output.
Power Analog supply voltage.
GND Analog ground.
Power Digital supply voltage.
GND Digital ground.
Input Comparator inputs. To power down the comparator, connect both of these pins to the analog
power supply. This will conserve ~4mA of current.
NC No connect.
2
FN4901.3
January 19, 2010