ISL26102 Datasheet, PDF (9/21 Pages) Intersil Corporation – Low-Noise 24-bit Delta Sigma ADC

ISL26102, ISL26104
Circuit Description
A key element in the ISL26102/ISL26104 A/D converters is its
low noise chopper-stabilized programmable gain amplifier. The
amplifier features seven gain settings (2x, 4x, 8x, 16x, 32x, 64x,
and 128x). On these gain settings, the amplifier has very high
input impedance but has restricted common mode range, which
does not extend all the way to the power supply rails. When the
gain of 1x is selected, the chopper-stabilized amplifier is
bypassed. The modulator input, which is used directly in 1x gain,
has a common mode range that extends to the supply rails. But,
because of this greater common mode range on the 1x gain
setting, the input current is higher than on the other gain
settings.
The ISL26102 provides the user with two fully differential signal
inputs at the multiplexer plus two other internal channel
selections, which allow the user to monitor the analog supply
voltage of the chip, and the on-chip temperature sensor. The
ISL26104 provides the user with two additional fully differential
inputs on the multiplexer.
The programmable gain amplifier has a passive RC filter on its
output. The resistors are located inside the chip on the outputs of
the differential amplifier stages. The capacitor (nominally a
100nF C0G ceramic or PPS film (Polyphenylene sulfide)) for the
filter is connected to the two CAP pins of the chip. The outputs of
the differential amplifier stages of the PGA are filtered before
their signals are presented to the delta-sigma modulator. This
filter reduces the amount of noise by limiting the signal
bandwidth and eliminating the chopping artifacts of the chopped
PGA stage.
Figure 7 illustrates a block diagram of the programmable gain
amplifier.
Functional Description
Analog Input Span
The input span of the A/D converter is determined by the
magnitude of the voltage reference and the gain setting
selection. The voltage reference magnitude is determined by the
voltage difference between the VREF+ and the VREF- pins. This
voltage may be as low as 1.5V or as great as the analog supply
voltage to the chip. The voltage on the VREF pins is scaled to accept
a voltage into the A/D converter on 1x gain of ±0.5 VREF/GAIN
where gain is 1. An illustration of the input span when using a 5V
V_REF is in Figure 8. The figure illustrates that with a V_REF = 5V and a
gain setting of 1x, the input span will be ±2.5V, which is a fully
differential signal. If the programmable gain amplifier gain is set to
another value other than 1x, the input span will be reduced by the
gain scale factor. With a V_REF = 5V and the PGA gain set at 128x,
the input span into the ADC will be [±(0.5)5V]/128 = ±19.53mV on
a fully differential basis.
5.00
4.50
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
2.500
AIN+
AIN-
VCM
2.500
FIGURE 8. DIFFERENTIAL INPUT FOR V_REF = 5V, GAIN = 1X
Digital Filter
The output of the delta-sigma modulator in the A/D converter is
filtered with a Sinc⁴ digital filter that includes programmable
decimation to achieve a wide range of output word rates. The
transfer function of the Sinc⁴ filter is illustrated in Figure 9.
Figure 9 is normalized to 1 being the output word rate. The
output word rate can be selected by setting bits in the OWR
(Output Word Rate) Register. The converter provides a wide
selection of word rates as shown in Table 3. Note that the word
rates are based upon an XTALIN/CLOCK of 4.9152MHz. If the
clock is a different frequency than 4.9152MHz, the actual output
word rate will scale proportionally.
TABLE 3. OUTPUT WORD RATE REGISTER SETTINGS
DATA RATE (Sps)
REGISTER CODE (Hex)
2.5
00
5
01
10
02
20
03
40
04
80
05
100
0B
160
06
200
0C
320
07
400
0D
640
08
800
0E
1000
11
1280
09
1600
0F
2000
12
2560
0A
3200
10
4000
13
9
FN7608.0
October 12, 2012