ISL26102 Datasheet, PDF (13/21 Pages) Intersil Corporation – Low-Noise 24-bit Delta Sigma ADC

ISL26102, ISL26104
NAME
PGA Gain
Conversion
Control
Delay Timer
PGA Offset
Array
(High Byte)
TABLE 4. CONTROL REGISTERS (Continued)
ADDRESS
DATA BITS
NOTES
97h 17h b2 b1 b0
000 = 1x
001 = 2x
010 = 4x
011 = 8x
100 = 16x
101 = 32x
110 = 64x
111 = 128x
PGA Gain Setting for Channel Pointed to by the Channel Pointer Register.
Whenever the Analog Supply Monitor or the Temp Sensor are selected, the PGA
gain is set to 1x.
84h 04h b2
0 = Off
Performing Offset Calibration has priority over instructions from bits b1b0
1 = Perform Offset Calibration
b1 b0
00 = Stop Conversions
01 = Perform Single Conversion
10 = Perform Continuous Conversions
11 = Not Used
C2h 42h b7-b0 The start of conversion is delayed
by: Delay = Register Word*4ms + 100µs
BDh 3Dh Offset Calibration Result
Most Significant Byte
For PGA Pointed to by PGA Pointer Register
PGA Offset BEh
Array
(Mid Byte)
PGA Offset BFh
Array
(Low Byte)
PGA Monitor Bch
3Eh Offset Calibration Result
Middle Byte
3Fh Offset Calibration Result
Low Byte
3ch b2 b1 b0
000 = 1x
001 = 2x
010 = 4x
011 = 8x
100 = 16x
101 = 32x
110 = 64x
111 = 128x
For PGA Pointed to by PGA Pointer Register
For Channel Pointed to by Channel Pointer Register
This register points to the offset register associated with the PGA gain selection
Writing to On-chip Registers
Writing into a register on the chip involves writing an address
byte followed by a data byte. The lead bit of the address byte is
always a logic 1 to indicate that data is to be written. The
remaining seven bits of the address byte contain the address of
the register that is to be written. To begin the write cycle, CS must
first be taken low with SCLK low. This should occur at least
125ns before SCLK goes high. This is shown as t_cs in the timing
diagram of Figure 11. Once CS is low, the user must then present
the lead bit to the SDI port. The data bits will be latched into the
port by rising edges of SCLK. The data set-up time (t_ds) of the
data bits to the rising edge of SCLK is 50ns (Note that one half
clock cycle of the highest SCLK rate is 1/(2*4 MHz) = 125ns).
Data hold time (t_dh) is also 50ns. Data bits should be advanced
to the next bit on falling edges of SCLK. Once the eight data bits
have been written, CS should be returned to high. (CS must be
high to read conversion data words from the port). When CS goes
high the user should ignore any activity on the SDO/RDY pin for
at least 10 cycles of the master clock, which is driving the ADC.
See Figure 11 for an illustration of the timing to write on-chip
registers.
If multiple registers are to be written, CS should be taken high
after each address byte/data byte combination and remain high
for at least a period of time equal to 6*1/(Xtal/Clock) frequency.
If the chip is operating from a 4.9152MHz master clock, this
would mean that CS should remain high between write cycles for
at least 6*1/4.9152MHz = 1.22µs.
Lower frequency master clock rates (minimum master clock rate
can be as low as 300kHz) will require CS to remain high for a
longer period of time between register write cycles.
Each time an address/data byte combination is written into the
port, the master clock is used to place the data into the register
after CS returns high. This is required because the data transfer
must be synchronized to the clock that is driving the
modulator/filter circuitry.
Reading from On-chip Registers
Reading from a register on the chip begins by writing an address
byte into the SDI port. The lead bit of the address byte is always a
13
FN7608.0
October 12, 2012