ISL26102 Datasheet, PDF (10/21 Pages) Intersil Corporation – Low-Noise 24-bit Delta Sigma ADC

ISL26102, ISL26104
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
-200
0.10
1.00
10.00
NORMALIZED FREQUENCY (1.00 = OWR)
FIGURE 9. TRANSFER FUNCTION OF SINC⁴ NORMALIZED TO
1 = OUTPUT WORD RATE
Digital Filter Settling Time
If the Input Mux Selection register is written into to select a new
channel, the modulator and the digital filter are reset and the
converter begins computing a new output word when the new
mux selection is made. The first conversion word output from the
A/D after a new mux channel is selected, or after the PGA gain is
changed, will be delayed to allow the filter to fully settle. A Sinc⁴
filter takes four conversion times to fully settle, therefore the
SDO/RDY signal will not fall until a time of four normal
conversion periods has elapsed. The SDO/RDY output falls to
signal that an output conversion word is ready to be read.
Whenever the input signal has a large step change in value, it
may take as many as six output conversions for the output word
to accurately represent the new input value.
Clock Sources
The ISL26102/ISL26104 can operate from an internal oscillator,
and external clock source, or from a crystal connected between
the XTALIN/CLOCK and XTALOUT pins. See the block diagram for
the clock system in Figure 10. When the converter is powered up,
the CLOCK DETECT block determines if an external clock source
is present. If a clock signal greater than 300kHz is present on the
XTALIN/CLOCK pin, the circuitry will disable the internal oscillator
and use the external clock as the clock to drive the chip circuitry.
If the ADC is to be operated from the internal oscillator the
XTALIN/CLOCK pin should be grounded. If the ADC is to be
driven with an external clock there should be a 100Ω resistor
placed in series with the clock signal to the XTALIN/CLOCK pin.
This helps slow the rise and fall time edges, which can impact
converter performance. If the ADC is to be operated with a
crystal, the crystal should be located very close to the A/D
converter package pins. Note that loading capacitors for the
crystal are not required as there are loading capacitors built into
the silicon, although the capacitor values are optimized for
operation with a 4.9152MHz crystal.
XTALIN/
CLOCK
CRYSTAL
OSCILLATOR
CLOCK DETECT
XTALOUT
MUX
INTERNAL
EN
OSCILLATOR
TO ADC
FIGURE 10. CLOCK GENERATOR BLOCK DIAGRAM
Overview of Registers and A/D Converter
Operation
The ISL26102, ISL26104 devices are controlled via their serial
port by accessing various on-chip registers. Communication to
the A/D via the serial port occurs by writing a command byte
followed by a data byte. All registers in the converter are
accessed or written as 8-bit wide registers, even though some
data words may be up to three bytes in length. The converter has
offset registers (three bytes wide) associated with each PGA gain
setting. These registers hold the offset calibration word, a three
byte twos complement word, for each gain selection. When
power is first applied to the converter these registers are reset to
zero. Note that the ISL26102, ISL26104 converters do not have
gain calibration registers for the PGA gains. This is because the
gain for each PGA gain setting is calibrated at the factory.
Table 4 list the registers inside the ADC. When power is first
applied the Offset Array Registers, registers which hold the offset
calibration words for each PGA gain, are set to zero.
The Chip ID register has a bit, which allows the user to identify
whether the chip is an ISL26102 (2 channel) or an ISL26104
(4 Channel) device. This register also has a code, which is
assigned to reveal the revision of the chip.
The SDO/LSPS register allows the user to control the behavior of
the SDO (Serial Data Output) output. If bit (b1) is set to logic 0,
the SDO/RDY output will go low when conversions are completed
and output the 24-bit conversion word if CS is taken high and 24
SCLKs are issued to the SCLK pin. If the SDO bit in this register is
set to logic 1, the SDO output will be set to a tri-state condition
(high output impedance). This allows another device, such as
another A/D converter, to be connected to this same signal line
going to the microcontroller.
The LSPS (Low-Side Power Switch) bit allows the user to toggle a
switch via the LSPS pin that can be used to enable power to a
load cell or other circuitry. When the LSPS bit is logic 0 the LSPS
switch is open. When the LSPS bit is logic 1, the switch is closed.
The LSPS bit is set back to a logic 0 if the chip is put into Standby
via the Standby Register, or if the PDWN signal is activated. See
data sheet tables for the current capability of the switch.
The Standby register has a bit which when set to logic 1, the chip
enters the standby mode. In standby mode, the chip enters a low
power state. Only the crystal oscillator is left powered (if used) to
enable a quick return to full operation when bit (b0) is set back to
logic 0. If the crystal is not being used, it is not powered. In this
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FN7608.0
October 12, 2012