ISL26102 Datasheet, PDF (17/21 Pages) Intersil Corporation – Low-Noise 24-bit Delta Sigma ADC

ISL26102, ISL26104
signal that a conversion data word is available. The Chip ID
register (read only), the Channel Pointer register, and the PGA
Monitor register can be read or written without any effect to the
filter, and therefore there will be no delay in SDO/RDY falling. If
the Standby register is enabled, conversions will be stopped.
Performing Calibration
The offset calibration function in the A/D converter removes the
offset associated with the PGA (Programmable Gain Amplifier) in
a specific gain setting. There are eight gain settings (1x, 2x, 4x,
8x, 16x, 32x, 64x, and 128x) and there is an array of eight sets of
three byte registers which hold the high, middle, and low bytes of
a 24-bit calibration word. The word is stored in twos complement
format.
When calibration is performed it is to correct the PGA offset and is
not actually associated with a given input channel. When a
calibration is executed, its result is based upon the results of the
converter performing a conversion with the input to the PGA shorted
internally to the chip. The conversion result will have an uncertainty
due to the peak-to-peak noise of the converter on the word rate in
which the calibration is performed. Lower word rates have lower
signal bandwidth and therefore will have less peak to peak variation
in the output result when a calibration is performed. Therefore, it
can improve calibration accuracy if the calibration is performed with
the lowest word rate acceptable to the user.
Perform a PGA Offset Calibration
1. Write to the Output Word Rate register (85h) and select a
word rate.
2. Write to the Input Mux Selection register (87h) and select an
input channel (AIN1 to AIN4, not AVDD monitor or
Temperature Sensor). Note that the channel will actually be
shorted internally so it need not be a specific channel.
3. Write to the Channel Pointer register (88h) with the same
selection written into the Mux Selection register.
4. Write the PGA gain selection into the PGA Gain register (97h).
5. Write bits b1 and b0 of the Conversion Control Register (84h)
setting b1 to logic 1 and bit b2 to logic 0 to Perform
Continuous Conversions.
6. Allow some delay and then write bit b2 of the Conversion Control
Register (84h) to logic 1 to start the calibration process. The
calibration time will be a function of the selection made in the
Output Word Rate register. To determine when the calibration
cycle is completed the user has two options. One is to monitor
SDO/RDY for a falling edge as this signals the completion of
conversion. A second approach would be to introduce a wait
timer for at least the period of five conversion times at the word
rate selected. [Example: If the word rate is 10Sps the calibration
should be completed at 5x 1/10s or 500ms. After this time, the
microcontroller can poll bit 2 of the Conversion Control Register.
Bit b2 will be set back to logic 0 when the calibration has
completed. It is best not to poll the register continuously because
the added activity on the serial port may introduce noise and
impact the calibration result.
Read Offset Calibration Registers
After an offset calibration has been performed, the calibration
result, which is a 24-bit (3 bytes) two's complement word, is stored
in the PGA Offset Arrays. Some user applications prefer to calibrate
their system in the factory, then off load the calibration data and
write it into non-volatile memory. Then when the product is powered
up, this data is written back into the registers of the ADC.
1. Write into the PGA Pointer register (BCh) the selection wanted
for the Gain of the PGA.
2. Read the three different PGA Offset Array registers, High byte
(3Dh), Mid byte(3Eh), and Low byte(3Fh). Note that they can
be read in any order, just understand that the three bytes
represent a two's complement 24-bit word with the byte in
order, high, mid and low.
Write Offset Calibration Registers
Upon power-up the offset registers are initialized to zero. After an
offset calibration is performed the registers associated with that
selected PGA gain will contain a valid 24-bit two's complement
number.
This number can be saved into non-volatile memory and then
written back to the PGA Offset Array register.
1. Write into the PGA Pointer register (BCh) the selection for the
Gain setting of the PGA for which offset data is to be written.
2. Write the three different PGA Offset Array registers, High byte
(BDh), Mid byte (BEh), and Low byte (BFh). Note that they can
be written in any order, just understand that the three bytes
represent a two's complement 24-bit word with the byte in
order, high, mid and low.
The value written will be subtracted from the conversion data before
it is output from the converter whenever that particular PGA Gain
setting is used. Offset values up to the equivalent of full scale of the
converter can be written but realize that this can consume dynamic
range for the actual signal if the offset value is set to a large
number.
Example Command Sequence
Table 7 illustrates an example command sequence to set up the
ADC once power supplies are active. The sequence of commands,
Set Channel Pointer, Set PGA Gain Setting, Set Mux Selection, Set
Data Rate, and Start Continuous Conversions, can be written into
the ADC as a sequence, each framed with CS going low at the
beginning of each command and returning high at the end of the
associated data byte (the rising edge of CS is the signal that actually
writes the data byte to the control register). After continuous
conversions are started, it is best if a time delay occur before the
Perform Offset Calibration is issued. There is no specific amount of
delay time as this depends upon the gain selection and the accuracy
required. When the command to perform the offset calibration is
issued, the continuous conversions in progress will be paused and
the conversion sequence will be performed as necessary to perform
the calibration. Once the calibration is completed, continuous
conversions will be automatically restarted. Any subsequent
commands which write into registers [SDO/LSPS, Output Word
Rate, Input Mux Selection, PGA Gain, Delay Timer, PGA Offset Array,
or Offset Calibration] while continuous conversions are in
progress will reset the digital filter and introduce a delay
determined by Equation 1 on page 11, after which, the SDO/RDY
signal will toggle low to signal the availability of a conversion
word.
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FN7608.0
October 12, 2012