ISL26102 Datasheet, PDF (16/21 Pages) Intersil Corporation – Low-Noise 24-bit Delta Sigma ADC

ISL26102, ISL26104
Device Supply and Temperature Monitoring
One of the multiplexer input selections is the AVDD Monitor. This
option allows the A/D converter to measure a divided down value
of the AVDD voltage. The nominal output code from AVDD
monitor is given by (2²³)*AVDD/(2*VREF). Table 6 provides a
listing of the nominal count of the A/D converter associated with
supply voltage values between 4.75 and 5.25V. Table 6 is based
on V_REF = 5V.
If a V_REF of 2.5V is used, the output code from the A/D converter
will stay at +Full Scale when AVDD > 5V. Thus, the AVDD monitor
will not be able to check the voltages greater than 5V, but it will
provide proper readings for AVDD voltages below 5V.
TABLE 6. ANALOG SUPPLY MONITOR OUTPUT CODES OVER SUPPLY
VOLTAGES (V_REF = 5.0V)
AVDD
(V)
OUTPUT CODE
(±5%)
5.25
4407063
5.10
4281464
5.00
4197996
4.90
4114662
4.75
3989915
AIN1 +
AIN1 -
AIN2 +
AIN2 -
AIN3 +
AIN3 -
AIN4 +
AIN4 -
+ _{TO BUFFER/PGA}
- ^{24-BIT ADC}
TEMP
SENSOR
AVDD
FIGURE 16. INPUT MULTIPLEXER BLOCK DIAGRAM
When the Input Mux Selection register is instructed to select the
on-chip temperature sensor signal, the A/D measures a
differential voltage produced between two diodes that are biased
at different operating currents. The differential voltage is defined
by Equation 2:
ΔV = 102.2 mV + (379µV* T(°C))
(EQ. 2)
Whenever the temperature sensor is selected in the Input Mux
Selection Register, the Gain is set to 1x.
At a temperature of +25°C the measured voltage will be
approximately 111.7mV. The actual output code from the
converter will depend upon the magnitude of the VREF signal.
The 111.7mV signal will be a portion of the span set by the VREF
voltage using a gain setting of 1x. If V_REF is 5V, one code in the
converter will be ±0.5(V_REF)/2²³ = 298nV. Since the converter
span is bipolar, and its span represents ± 8.338 million codes,
the +111.7mV will output of a code of approximately 374,800
counts.
The on-chip temperature will typically be about 3° hotter than
ambient because the device's power consumption is about
50 mW and the thermal impedance from die to ambient is about
63°/W; (0.05)*63 = 3.15°.
Getting Started
When power is first applied to the converter, the PDWN pin
should be held low until the power supplies and the voltage
reference are stable. Then PDWN should be taken high. When
this occurs the serial port logic and other logic in the chip will
have been reset. The chip contains factory calibration data stored
in on-chip non-volatile memory. When PDWN goes positive this
data is transferred into the appropriate working registers. This
initialization can take up to 12.6ms. If an external clock or the
internal oscillator are used as the clock for the chip, then this
12.6ms time includes the time necessary for these to be
functional. But, if the crystal oscillator is used, the crystal may
take 20ms to start up before the 12.6ms initialization occurs.
Writing into or reading from the serial port should be delayed
until the clock source and the initialization period have elapsed.
Once the clock source and initialization period have elapsed, the
user should configure the ADC by writing into the appropriate
registers. The commands and the corresponding data bytes that
are to be placed into each of the registers are shifted into the SDI
pin with CS held low. CS should be taken high for at least six
cycles of the master clock after each command/data byte
combination. This allows the control logic to properly synchronize
the writing of the register with the master clock that controls the
modulator/filter system. Each command/data byte combination
should have its own CS cycle of CS going low, shifting the data,
then CS going high, and remaining high for at least six cycles of
the master clock.
Even though the device has been powered up, reset, and its
register settings have been configured, the programmable gain
amplifier and modulator portions of the ADC remain in a low
power state until a command to start conversions is written into
the Conversion Control register. To minimize drift in the device
due to self-heating, it is recommended that after all registers are
initialized to their initial condition, the command to start
continuous conversions be issued as soon as is practical.
Subsequent changes to registers, such as selecting another mux
channel, should be performed with continuous conversions
active. The proper method of writing to the other registers when
continuous conversions are active is to wait for SDO/RDY to fall,
read the conversion data, then take CS low and issue the
command and the data byte that is to be written into a register,
then return CS high. If multiple registers are to be written, CS
should be toggled low and high to frame each command/data
byte combination. Whenever any of the following registers
[SDO/LSPS, Output Word Rate, Input Mux Selection, PGA Gain,
Delay Timer, PGA Offset Array, or Offset Calibration] are written
with continuous conversions in progress, the digital filter will be
reset and there will be a delay determined by Equation 1 on
page 11. The delay will begin when CS returns and remains high.
When the delay has elapsed, the SDO/RDY signal will go low to
16
FN7608.0
October 12, 2012