ISL26102 Datasheet, PDF (5/21 Pages) Intersil Corporation – Low-Noise 24-bit Delta Sigma ADC

ISL26102, ISL26104
Electrical Specifications V_REF+ = 5.0V, V_REF- = 0V, A_VDD = 5V, D_VDD = 5V XTALIN/CLOCK = 4.9152MHz (Note 6)
T_A = -40°C to +105°C, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +105°C. (Continued)
SYMBOL
PARAMETER
TEST LEVEL OR NOTES
MIN
MAX
(Note 7)
TYP
(Note 7)
UNITS
VOLTAGE REFERENCE INPUT
VREF
VREF+
VREF-
VREFI
Voltage Reference Input
Positive Voltage Reference Input
Negative Voltage Reference Input
Voltage Reference Input Current
VREF = VREF+ - VREF-
1.5
5.0
A_VDD + 0.1
V
V_REF- + 1.5
A_VDD + 0.1
V
A_GND - 0.1
V_REF+ - 1.5
V
350
nA
Low-Side Power Switch
r_ON ON-resistance
Continuous Current
10
Ω
30
mA
Power Supply Requirements
A_VDD
D_VDD
A_IDD
Analog Supply Voltage
Digital Supply Voltage
Analog Supply Current
Gain of 1
Gain = 2 to 128
4.75
5.0
5.25
V
2.7
5.0
5.25
V
6
10
mA
9
12
mA
Power-down
0.2
2.5
µA
Standby
0.3
µA
D_IDD Digital Supply Current
Gain of 1
Gain = 2 to 128
750
950
µA
750
950
µA
Power-down
1
26
µA
Standby
1.8
µA
Power
Normal
Gain = 1
33.75
54.75
Gain = 2 to 128
48.75
64.75
mW
Power-down
6
µW
Standby
10.5
µW
Digital Inputs
V_IH
V_IL
V_OH
V_OL
Input Leakage Current
I_OH = -1mA
I_OL = 1mA
0.7 D_VDD
D_VDD - 0.4
V
0.2 D_VDD
V
V
0.2 D_VDD
V
±10
µA
External Clock Input Frequency
0.3
4.9152
MHz
Serial Clock Input Frequency (Note 9)
4
MHz
NOTES:
6. If the device is driven with an external clock, best performance will be achieved if the rise and fall times of the clock are slowed to less than 20ns
(10% to 90% rise/fall time).
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
8. Output word rates (MIN and MAX in the table) are specified using 4.9152MHz clock. If a different clock frequency is used, or if the internal oscillator
is used as the clock source for the converter, the output word rates will scale proportionally to the change in the clock frequency.
9. The OWR (Output Word Rate) setting dictates the rate at which the SDO/RDY signal will fall. To read every conversion word, reading of the conversion
word should begin immediately after SDO/RDY falls and the SCLK rate should be fast enough to read all 24 data bits of the conversion word before
the next falling edge of SDO/RDY that indicates that a new conversion word is available.
5
FN7608.0
October 12, 2012