80C286883 Datasheet, PDF (9/13 Pages) Intersil Corporation – High Performance Microprocessor with Memory Management and Protection

80C286/883
Waveforms
BUS CYCLE TYPE
V_OH
CLK
T_I
3 _φ2
2
12A
V_OL
READ CYCLE
ILLUSTRATED WITH ZERO
WAIT STATES
T_S
T_C
1
φ2
φ1
φ2
12B
WRITE CYCLE
ILLUSTRATED WITH ONE
WAIT STATE
T_S
T_C
φ1
φ2
φ1
φ2
T_C
φ1
φ2
READ
(T_I OR T_S)
φ1
S1 • S0
A₂₃ - A₀
M/IO,
COD INTA
BHE, LOCK
D₁₅ - D₀
READY
19
13
19
13
VALID ADDRESS
13
VALID CONTROL
VALID ADDRESS
13
VALID CONTROL
VALID IF T_S
9
14
8
VALID READ DATA
11
10
15
VALID WRITE DATA
11
10
SRDY +
SRDYEN
ARDY +
ARDYEN
PCLK
ALF
CMDLY
MWTC
12
11
19
19
16
17
12
13
19
20
14
13
13
12
13
12
29
30
MRDC
DT/R
29
30
19
(SEE NOTE 1)
22
24
20
21
23
DEN
NOTES:
1. The modified timing is due to the CMDLY signal being active.
2. 82C254 and 82C288 Timing Waveforms are shown for reference only, and no guarantee is inplied.
FIGURE 2. MAJOR CYCLE TIMING
136