80C286883 Datasheet, PDF (12/13 Pages) Intersil Corporation – High Performance Microprocessor with Memory Management and Protection

Waveforms (Continued)
80C286/883
BUS CYCLE TYPE
V_CH ^TI φ2
CLK
V_CL
S1 • S0
CLK
A₂₃ -A₀
M/IO,
COD INTA
12A
PEACK
PEREQ
φ1 ^TS φ2
1 ^{TC φ2}
φ1 ^TS φ2
φ1 ^TC φ2
φ1 ^TI
I/0 READ IF PROC. EXT. TO MEMORY
MEMORY READ IF MEMORY TO PROC. EXT
MEMORY WRITE IF PROC. EXT. TO MEMORY
I/O WRITE IF MEMORY TO PROC. EXT.
MEMORY ADDRESS IF PROC. EXT. TO MEMORY TRANSFER I/O
PORT ADDRESS 00FA(H) IF MEMORY TO PROC. EXT. TRANSFER
12B
(SEE NOTE 1)
(SEE NOTE 2)
4
I/O PORT ADDRESS 00FA(H) IF PROC. EXT. TO MEMORY TRANSFER
MEMORY ADDRESS IF MEMORY TO PROC. EXT. TRANSFER
5
NOTES:
1. PEACK always goes active during the first bus operation of a processor extension data operand transfer sequence. The first bus operation
will be either a memory read at operand address or I/O read at port address 00FA(H).
2. To prevent a second processor extension data operand transfer, the worst case maximum time (shown above) is 3 x 1 - 12A_MAX -(4)_MIN
The actual, configuration dependent, maximum time is: 3 x
1
-
12A_MAX
-
(4)
MIN
+N
x
2
x
(1)_.
N
is
the
number
of
extra
T_C
states
added
to either the first or second bus operation of the processor extension data operand transfer sequence.
FIGURE 6. 80C286/883 PEREQ/PEACK TIMING FOR ONE TRANSFER ONLY
BUS CYCLE TYPE
V_CH
CLK
V_CL
RESET
S1 • S0
PEACK
A₂₃ - A₀
BHE
M/IO
COD/INTA
LOCK
DATA
HILDA
φ2
φ1 ^TX φ2
φ1 ^TX φ2
φ1 ^TX φ2
φ1 ^TI φ2
6
(SEE NOTE 1)
(SEE NOTE 2) ₇
6
AT LEAST
16 CLK PERIODS
12B
UNKNOWN
13
UNKNOWN
UNKNOWN
UNKNOWN
13
13
15
(SEE NOTE 3)
16
UNKNOWN
NOTES:
1. Setup time for RESET ↑ may be violated with the consideration that φ1 of the processor clock may begin one system CLK period later.
2. Setup and hold times for RESET ↓ must be met for proper operation, but RESET ↓ may occur during φ1 or φ2.
3. The data bus is only guaranteed to be in a high impedance state at the time shown.
BUS CYCLE TYPE
CLK
FIGURE 7. INITIAL 80C286/883 PIN STATE DURING RESET
BUS HOLD ACKNOWLEDGE
T_H
φ1 φ2
T_H
φ1 φ2
T_H
φ1 φ2
WRITE CYCLE
T_S
φ1 φ2
139
T_C
φ1 φ2
T_C
φ1 φ2
T_C
φ1 φ2
(SEE NOTE 5)
BUS HOLD
ACKNOWLEDGE
T_I
φ1 φ2
T_H
φ1 φ2