80C286883 Datasheet, PDF (10/13 Pages) Intersil Corporation – High Performance Microprocessor with Memory Management and Protection

Waveforms (Continued)
80C286/883
BUS CYCLE TYPE
CLK
PCLK
(SEE NOTE 1)
V_CH
V_CL
INTR, NMI
HOLD, PEREQ
(SEE NOTE 2)
4
ERROR, BUSY
(SEE NOTE 2)
φ1 ^TX
φ2
19
19
5
4
5
V_CH
φ2
CLK
V_CL
RESET
V_CH
CLK
V_CL
RESET
φ1 ^TX φ1
φ2
7
6
(SEE NOTE 1)
T_X
φ1
φ2
φ2
7
(SEE NOTE 1)
6
NOTES:
1. PCLK indicates which processor cycle phase will occur on the
next CLK. PCLK may not indicate the correct phase until the first
cycle is performed.
2. These inputs are asynchronous. The setup and hold times shown
assure recognition for testing purposes.
NOTE:
1. When RESET meets the setup time shown, the next CLK will
start or repeat φ1 of a processor cycle.
FIGURE 3. 80C286/883 ASYNCHRONOUS INPUT SIGNAL
TIMING
FIGURE 4. 80C286/883 RESET INPUT TIMING AND SUBSE-
QUENT PROCESSOR CYCLE PHASE
137