80C286883 Datasheet, PDF (5/13 Pages) Intersil Corporation – High Performance Microprocessor with Memory Management and Protection

80C286/883
TABLE 2. 80C286/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
AC Timings are Referenced to 0.8V and 2.0V Points of the Signals as Illustrated in Datasheet Waveforms, Unless Otherwise Noted. Device
Guaranteed and 100% Tested.
80C286/883
PARAMETER
HLDA Valid Delay
(Note 5)
SYMBOL
CONDITIONS
15
V_CC = 4.5V and
5.5V, C_L = 100pF
IL = |2mA|
GROUP A
SUBGROUPS TEMPERATURE
10MHz
12.5MHz
MIN MAX MIN MAX UNITS
9, 10, 11
-55^oC ≤ T_A ≤ +125^oC 0
47
0
25
ns
NOTES:
1. Asynchronous inputs are INTR, NMI, HOLD, PEREQ, ERROR, and BUSY. This specification is given only for testing purposes, to assure
recognition at a specific CLK edge.
2. Delay from 1.0V on the CLK to 0.8V or 2.0V.
3. Delay from 1.0V on the CLK to 0.8V for Min (HOLD time) and to 2.0V for Max (inactive delay).
4. Delay from 1.0V on the CLK to 2.0V for Min (HOLD time) and to 0.8V for Max (active delay).
5. Delay from 1.0V on the CLK to 2.0V.
TABLE 3. 80C286/883 ELECTRICAL PERFORMANCE SPECIFICATIONS
80C286/883
10MHz
12.5MHz
PARAMETER
SYMBOL CONDITIONS NOTES
TEMPERATURE MIN MAX MIN MAX UNITS
CLK Input Capacitance
C_CLK
FREQ = 1MHz
5
T_A = +25^oC
-
10
-
10
pF
Other Input Capacitance
C_IN
FREQ = 1MH
5
T_A = +25^oC
-
10
-
10
pF
I/O Capacitance
C_I/O
FREQ = 1MH
5
T_A = +25^oC
-
10
-
10
pF
Address/Status/Data
15
Float Delay
1, 3, 4, 5 -55^oC ≤ T_A ≤ +125^oC 0
47
0
32
ns
Address Valid to Status
19
I_L = | 2.0mA|
1, 2, 5 -55^oC ≤ T_A ≤ +125^oC 27
-
20
-
ns
SETUP Time
NOTES:
1. Output Load: C_L = 100pF.
2. Delay measured from address either reaching 0.8V or 2.0V (valid) to status going active reaching 0.8V or status going inactive reaching
2.0V.
3. Delay from 1.0V on the CLK to Float (no current drive) condition.
4. I_L = -6mA (V_OH to Float), I_L = 8mA (V_OL to Float).
5. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are char-
acterized upon initial design and after major process and/or design changes.
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
METHOD
SUBGROUPS
Initial Test
Interim Test
PDA
100%/5004
100%/5004
100%
-
1, 7, 9
1
Final Test
100%
2, 3, 8A, 8B, 10, 11
Group A
Group C & D
-
Samples/5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 7, 9
132