X96012 Datasheet, PDF (8/27 Pages) Intersil Corporation – Universal Sensor Conditioner with Dual Look Up Table Memory and DACs

X96012
2-WIRE INTERFACE A.C. CHARACTERISTICS
Symbol
f_SCL
t_IN(4)
t_AA(4)
t_BUF(4)
t_LOW
t_HIGH
t_SU:STA
t_HD:STA
t_SU:DAT
t_HD:DAT
t_SU:STO
t_DH
t_R(4)
Parameter
SCL Clock Frequency
Pulse width Suppression Time at
inputs
SCL Low to SDA Data Out Valid
Time the bus free before start of new
transmission
Clock Low Time
Clock High Time
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
Data In Hold Time
Stop Condition Setup Time
Data Output Hold Time
SDA and SCL Rise Time
t_F(4)
SDA and SCL Fall Time
t_SU:WP⁽⁴⁾
t_HD:WP⁽⁴⁾
Cb⁽⁴⁾
WP Setup Time
WP Hold Time
Capacitive load for each bus line
Min Typ Max Units
1⁽³⁾
400
kHz
50
ns
1300
900
ns
ns
1.3
0.6
600
600
100
0
600
50
20
+0.1Cb⁽¹⁾
20
+0.1Cb⁽¹⁾
600
600
1200⁽³⁾ µs
1200⁽³⁾ µs
ns
ns
ns
µs
ns
ns
300
ns
300
ns
ns
ns
400
pF
Test Conditions / Notes
See “2-Wire Interface Test
Conditions” (below),
See Figure 1, Figure 2 and
Figure 3.
2-WIRE INTERFACE TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times, between 10% and 90%
Input and Output Timing Threshold Level
External Load at pin SDA
10 % to 90 % of Vcc
10 ns
1.4V
2.3kΩ to Vcc and 100 pF to Vss
NONVOLATILE WRITE CYCLE TIMING
Symbol
Parameter
Min
Typ
Max Units Test Conditions / Notes
t_WC(2)
Nonvolatile Write Cycle Time
5
10
ms
See Figure 3
Notes: 1. Cb = total capacitance of one bus line (SDA or SCL) in pF.
2. t_WC is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It
is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
3. The minimum frequency requirement applies between a START and a STOP condition.
4. These parameters are periodically sampled and not 100% tested.
8
FN8216.0
March 10, 2005