X96012 Datasheet, PDF (12/27 Pages) Intersil Corporation – Universal Sensor Conditioner with Dual Look Up Table Memory and DACs

Figure 4. Control and Status Register Format
X96012
Byte
MSB
LSB
Register
Address
7
6
5
4
3
2
1
Name
0
80h
Non-Volatile
I2DS
I1DS
I1 and I2 Direction
0: Source
1: Sink
NV1234 ADCfiltOff ADCIN
VRM
BL1
BL0
Control 0
Control
1, 2, 3, 4
Volatility
0: Volatile
1: Non-
volatile
ADC
filtering
0: On
1: Off
ADC Input
0: Internal
1: External
Voltage
Reference
Mode
0: Internal
1: External
Block Lock
00: None Locked
01: GPM Locked
10: GPM, LUT1, Locked
11: GPM, LUT1, LUT2
Locked
81h
Volatile or
Non-Volatile
Direct Access to LUT1
Reserved Reserved
L1DA5
L1DA4
L1DA3
L1DA2
L1DA1
L1DA0
Control 1
82h
Volatile or
Non-Volatile
Direct Access to LUT2
Reserved Reserved
L2DA5
L2DA4
L2DA3
L2DA2
L2DA1
L2DA0
Control 2
83h
Volatile or
Non-Volatile
Direct Access to DAC1
D1DA7 D1DA6
D1DA5
D1DA4
84h
Volatile or
Non-Volatile
Direct Access to DAC2
D2DA7 D2DA6
D2DA5
D2DA4
D1DA3
D2DA3
D1DA2
D2DA2
D1DA1
D2DA1
D1DA0
D2DA0
Control 3
Control 4
85h
Non-Volatile
D2DAS L2DAS D1DAS L1DAS I2FSO1 I2FSO0
Direct
Access
to DAC2
0: Disabled
1: Enabled
Direct
Access
to LUT2
0: Disabled
1: Enabled
Direct
Access
to DAC1
0: Disabled
1: Enabled
Direct
Access
to LUT1
0: Disabled
1: Enabled
R2 Selection
00: External
01: Low Internal
10: Middle Internal
11: High Internal
I1FSO1 I1FSO0
R1 Selection
00: External
01: Low Internal
10: Middle Internal
11: High Internal
Control 5
86h
Volatile
WEL Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Write
Enable
Latch
0: Write
Disabled
1: Write
Enabled
ADC Output
87h
Volatile
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Control 6
Status
Registers in byte addresses 88h through 8Fh are reserved.
12
FN8216.0
March 10, 2005