X96012 Datasheet, PDF (26/27 Pages) Intersil Corporation – Universal Sensor Conditioner with Dual Look Up Table Memory and DACs

X96012
Figure 22. Read Sequence
S
Signals
t
from the
a
Master
r
t
Slave
Address
with
R/W=0
Address
Byte
S
Slave
t
Address
a
with
r
R/W=1
t
S
A
A
t
C
C
o
K
K
p
Signal at
SDA
10 10
Signals from
the Slave
0
A
C
K
10 10
A
C
K
1
A
C
K
First Read
Data Byte
Last Read
Data Byte
The Data Bytes are from the memory location indicated
by an internal pointer. This pointer initial value is deter-
mined by the Address Byte in the Read operation instruc-
tion, and increments by one during transmission of each
Data Byte. After reaching the memory location 10Fh the
pointer “rolls over” to 00h, and the device continues to
output data for each ACK received.
A Read operation internal pointer can start at any
memory location from 00h through FEh, when the
Address Byte is 00h through FEh respectively. But it
starts at location 100h if the Address Byte is FFh.
When reading any of the control registers 1, 2, 3, or 4,
the Data Bytes are always the content of the corre-
sponding nonvolatile cells, even if bit NV1234 is "0"
(See “Control and Status Register Format”).
Data Protection
There are four levels of data protection designed into
the X96012: 1- Any Write to the device first requires
setting of the WEL bit in Control 6 register; 2- The
Block Lock can prevent Writes to certain regions of
memory; 3- The Write Protection pin disables any writ-
ing to the X96012; 4- The proper clock count, data bit
sequence, and STOP condition is required in order to
start a nonvolatile write cycle, otherwise the X96012
ignores the Write operation.
WP: Write Protection Pin
When the Write Protection (WP) pin is active (LOW),
any Write operations to the X96012 is disabled, except
the writing of the WEL bit.
26
FN8216.0
March 10, 2005