X96012 Datasheet, PDF (23/27 Pages) Intersil Corporation – Universal Sensor Conditioner with Dual Look Up Table Memory and DACs

X96012
Slave Address Byte
Following a START condition, the master must output
a Slave Address Byte (Refer to figure 16.). This byte
includes three parts:
– The four MSBs (SA7 - SA4) are the Device Type
Identifier, which must always be set to 1010 in order
to select the X96012.
– The next three bits (SA3 - SA1) are the Device
Address bits (AS2 - AS0). To access any part of the
X96012’s memory, the value of bits AS2, AS1, and
AS0 must correspond to the logic levels at pins A2,
A1, and A0 respectively.
– The LSB (SA0) is the R/W bit. This bit defines the
operation to be performed on the device being
addressed. When the R/W bit is “1”, then a Read
operation is selected. A “0” selects a Write
operation (Refer to figure 16.)
Figure 17. Acknowledge Polling Sequence
Byte load completed by issuing
STOP. Enter ACK Polling
Issue START
Issue Slave Address
Byte (Read or Write)
Issue STOP
NO
ACK returned?
YES
High Voltage
complete. Continue command
sequence.
YES
Continue normal Read or Write
command sequence
NO
Issue STOP
PROCEED
Nonvolatile Write Acknowledge Polling
After a nonvolatile write command sequence is cor-
rectly issued (including the final STOP condition), the
X96012 initiates an internal high voltage write cycle.
This cycle typically requires 5 ms. During this time,
any Read or Write command is ignored by the
X96012. Write Acknowledge Polling is used to deter-
mine whether a high voltage write cycle is completed.
During acknowledge polling, the master first issues a
START condition followed by a Slave Address Byte.
The Slave Address Byte contains the X96012’s Device
Type Identifier and Device Address. The LSB of the
Slave Address (R/W) can be set to either 1 or 0 in this
case. If the device is busy within the high voltage
cycle, then no ACK is returned. If the high voltage
cycle is completed, an ACK is returned and the master
can then proceed with a new Read or Write operation.
(Refer to figure 17.).
Byte Write Operation
In order to perform a Byte Write operation to the mem-
ory array, the Write Enable Latch (WEL) bit of the Con-
trol 6 Register must first be set to “1”. (See “WEL:
Write Enable Latch (Volatile)” on page 14.)
For any Byte Write operation, the X96012 requires the
Slave Address Byte, an Address Byte, and a Data Byte
(See Figure 18). After each of them, the X96012
responds with an ACK. The master then terminates the
transfer by generating a STOP condition. At this time, if
all data bits are volatile, the X96012 is ready for the next
read or write operation. If some bits are nonvolatile, the
X96012 begins the internal write cycle to the nonvolatile
memory. During the internal nonvolatile write cycle, the
X96012 does not respond to any requests from the
master. The SDA output is at high impedance.
A Byte Write operation can access bytes at locations
00h through FEh directly, when setting the Address
Byte to 00h through FEh respectively. Setting the
Address Byte to FFh accesses the byte at location
100h. The other sixteen bytes, at locations FFh and
101h through 10Fh can only be accessed using Page
Write operations. The byte at location FFh can only be
written using a “Page Write” operation.
Writing to Control bytes which are located at byte
addresses 80h through 8Fh is a special case
described in the section “Writing to Control Registers” .
23
FN8216.0
March 10, 2005