X96012 Datasheet, PDF (25/27 Pages) Intersil Corporation – Universal Sensor Conditioner with Dual Look Up Table Memory and DACs

X96012
Figure 20. Example: Writing 12 bytes to a 16-byte page starting at location 11.
7 bytes
Address=0
Address=6
5 b5ybtyetess
Address=11
Address=7
Address Pointer
Ends Up Here
Address=15
The four registers Control 1 through 4, have a nonvol-
atile and a volatile cell for each bit. At power-up, the
content of the nonvolatile cells is automatically
recalled and written to the volatile cells. The content of
the volatile cells controls the X96012’s functionality. If
bit NV1234 in the Control 0 register is set to “1”, a
Write operation to these registers writes to both the
volatile and nonvolatile cells. If bit NV1234 in the Con-
trol 0 register is set to “0”, a Write operation to these
registers only writes to the volatile cells. In both cases
the newly written values effectively control the
X96012, but in the second case, those values are lost
when the part is powered down.
If bit NV1234 is set to “0”, a Byte Write operation to
Control registers 0 or 5 causes the value in the nonvol-
atile cells of Control registers 1 through 4 to be
recalled into their corresponding volatile cells, as dur-
ing power-up. This doesn’t happen when the WP pin is
LOW, because Write Protection is enabled. It is gener-
ally recommended to configure Control registers 0 and
5 before writing to Control registers 1 through 4.
When reading any of the control registers 1, 2, 3, or 4,
the Data Bytes are always the content of the corre-
sponding nonvolatile cells, even if bit NV1234 is "0"
(See “Control and Status Register Format”).
Read Operation
A Read operation consist of a three byte instruction
followed by one or more Data Bytes (See Figure 22).
The master initiates the operation issuing the following
sequence: a START, the Slave Address byte with the
R/W bit set to “0”, an Address Byte, a second START,
and a second Slave Address byte with the R/W bit set
to “1”. After each of the three bytes, the X96012
responds with an ACK. Then the X96012 transmits
Data Bytes as long as the master responds with an
ACK during the SCL cycle following the eigth bit of
each byte. The master terminates the read operation
(issuing a STOP condition) following the last bit of the
last Data Byte (See Figure 22).
Figure 21. Writing to Control Registers 1, 2, 3, and 4
Signals from
the Master
Signal at SDA
Signals from
the Slave
S
Write
t
a
Slave
r
Address
Address
Byte = 81h
t
Four Data Bytes
Data Byte for
Control 1
S
Data Byte for
t
Control 4
o
p
10 10
0 10 00 0 0 01
A
A
C
C
K
K
A
A
C
C
K
K
25
FN8216.0
March 10, 2005