X96012 Datasheet, PDF (6/27 Pages) Intersil Corporation – Universal Sensor Conditioner with Dual Look Up Table Memory and DACs

X96012
D/A CONVERTER CHARACTERISTICS (See pg. 4 for Standard Conditions)
Symbol
IFS₀₀
IFS₀₁
IFS₁₀
IFS₁₁
Offset_DAC
FSError_DAC
DNL_DAC
INL_DAC
V_ISink
V_ISource
I_OVER
I_UNDER
t_rDAC
TCO_I1I2
Parameter
I1 or I2 full scale current, with external
resistor setting
I1 or I2 full scale current, with internal
low current setting option
I1 or I2 full scale current, with internal
middle current setting option
I1 or I2 full scale current, with internal
high current setting option
I1 or I2 D/A converter offset error
I1 or I2 D/A converter full scale error
I1 or I2 D/A converter
Differential Nonlinearity
I1 or I2 D/A converter Integral Nonlin-
earity with respect to a straight line
through 0 and the full scale value
I1 or I2 Sink Voltage Compliance
I1 or I2 Source Voltage Compliance
I1 or I2 overshoot on D/A Converter
data byte transition
I1 or I2 undershoot on D/A Converter
data byte transition
I1 or I2 rise time on D/A Converter data
byte transition; 10% to 90%
Temperataure coefficient of output
current I1 or I2 when using internal
resistor setting
Min Typ
1.56 1.58
0.3 0.4
0.64 0.85
1 1.3
1
-2
-0.5
Max
1.6
3.2
0.5
1.06
1.6
1
2
0.5
Unit
mA
mA
mA
mA
mA
Test Conditions / Notes
See note 1, 5
See note 1, 4, 6
DAC input Byte = FFh,
Source or sink mode, V(I1)
and V(I2) are Vcc - 1.2V in
source mode and 1.2V in sink
mode.
See notes 2 and 3.
LSB
LSB
LSB
-1
1
LSB
1.2
Vcc
V See note 5
2.5
Vcc
V See note 4, 6
0
Vcc-1.2 V See note 5
0
Vcc-2.5 V See note 4, 6
0
µA DAC input byte changing from
00h to FFh and vice
0
µA
versa, V(I1) and V(I2) are
Vcc - 1.2V in source mode
and 1.2V in sink mode.
5
30
µs _{See note 4.}
±200
ppm/
°C
See Figure 8.
Bits I1FSO[1:0] ¦ 00₂ or
Bits I2FSO[1:0] ¦ 002,
VRMbit = “1”
Notes: 1. DAC input Byte = FFh, Source or sink mode.
[ ] ^{2. LSB is defined as}
2
3
x
V(VRef)
255
divided by the resistance between R1 or R2 to Vss.
3. Offset_DAC: The Offset of a DAC is defined as the deviation between the measured and ideal output, when the DAC input is 01h. It is
expressed in LSB.
FSError_DAC: The Full Scale Error of a DAC is defined as the deviation between the measured and ideal output, when the input is FFh. It
is expressed in LSB. The Offset_DAC is subtracted from the measured value before calculating FSError_DAC.
DNL_DAC: The Differential Non-Linearity of a DAC is defined as the deviation between the measured and ideal incremental change in
the output of the DAC, when the input changes by one code step. It is expressed in LSB. The measured values are adjusted for Offset
and Full Scale Error before calculating DNL_DAC.
INL_DAC: The Integral Non-Linearity of a DAC is defined as the deviation between the measured and ideal transfer curves, after adjust-
ing the measured transfer curve for Offset and Full Scale Error. It is expressed in LSB.
4. These parameters are periodically sampled and not 100% tested.
5. V(I1) and V(I2) are V_CC - 1.2V in source mode and 1.2V in sink mode. In this range the current at I1 or I2 varies < 1%.
6. The maximum current, sink or source, can be set with an external resistor to 3.2 mA with a minimum V_CC = 4.5V. The compliance
voltage changes to 2.5V from the sourcing rail, and the current variation is < 1%.
6
FN8216.0
March 10, 2005