X9252_14 Datasheet, PDF (8/19 Pages) Intersil Corporation – Quad Digitally-Controlled Potentiometer

X9252
Test Circuit
Equivalent Circuit
TEST POINT
R_W
FORCE
CURRENT
Principles of Operation
The X9252 is an integrated circuit incorporating four resistor
arrays, their associated registers and counters, and the
serial interface logic providing direct communication
between the host and the digitally controlled potentiometers.
This section provides detail description of the following:
- Resistor Array
- Up/Down Interface
- 2-wire Interface
Resistor Array Description
The X9252 is comprised of four resistor arrays. Each array
contains 255 discrete resistive segments that are connected
in series. The physical ends of each array are equivalent to
the fixed terminals of a mechanical potentiometer (R_Hi and
R_Li inputs) (see Figure 1).
At both ends of each array and between each resistor
segment is a switch connected to the wiper (R_Wi) pin.
R_TOTAL
R_H
R_L
C_H
C_W
C_L
R_W
Within each individual array only one switch may be turned
on at a time.
These switches are controlled by a Wiper Counter Register
(WCR). The 8 bits of the WCR (WCR[7:0]) are decoded to
select and enable one of 256 switches (see Table 1). Note
that each wiper has a dedicated WCR. When all bits of a
WCR are zeroes, the switch closest to the corresponding R_L
pin is selected. When all bits of a WCR are ones, the switch
closest to the corresponding R_H pin is selected.
The WCR is volatile and may be written directly. There are
four non-volatile Data Registers (DR) associated with each
WCR. Each DR can be loaded into WCR. All DRs and
WCRs can be read or written.
Power-Up and Down Requirements
During power-up, CS must be high, to avoid inadvertant
“store” operations. At power-up, the contents of Data
Registers DR00, DR10, DR20, and DR30, are loaded into
the corresponding wiper counter register.
i = 0, 1, 2, AND 3
FOUR
NON-VOLATILE
DATA
REGISTERS
DRi0, DRi1,
DRi2, and
DRi3
VOLATILE
8-BIT
WIPER
COUNTER
REGISTER
WCRi
WP
SCL
SDA
A2, A1, A0
CS
U/D
DS1, DS0
INTERFACE CONTROL AND
VOLATILE STATUS REGISTER (SR)
(SHARED BY THE FOUR DCPs)
WCR[7:0] ²⁵⁵
= FF hex
254
253
252
ONE
OF
256
DECODER
2
1
WCR[7:0]
0
= 00 hex
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8
FIGURE 1. DETAILED BLOCK DIAGRAM OF ONE DCP
R_Hi
R_Li
R_Wi
FN8167.3
July 24, 2014