X9252_14 Datasheet, PDF (5/19 Pages) Intersil Corporation – Quad Digitally-Controlled Potentiometer

X9252
Endurance and Data Retention
PARAMETER
Minimum Endurance
Data Retention
MIN
100,000
100
UNITS
Data changes per bit
Years
Capacitance
Symbol
Test
Test Conditions
Max
C_IN/OUT (Note 7) Input/Output Capacitance (SDA)
V_OUT = 0V
8
C_IN (Note 7) Input Capacitance (SCL, WP, DS0, DS1, CS, U/D, A2, A1 and
V_IN = 0V
6
A0)
UNITS
pF
pF
Power-Up Timing
SYMBOL
PARAMETER
t_D (Notes 7, 11) Power-Up Delay from V_CC Power-Up (V_CC above 2.7V) to Wiper Position Recall
Completed, and Communication Interfaces Ready for Operation.
MAX
2
UNITS
ms
A.C. Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Threshold Level
External Load at Pin SDA
2-Wire Interface Timing (s)
SYMBOL
PARAMETER
f_SCL
t_HIGH
t_LOW
t_SU:STA
t_HD:STA
t_SU:STO
t_SU:DAT
t_HD:DAT
t_R (Note 7)
t_F (Note 7)
t_AA (Note 7)
t_DH
t_IN (Note 7)
t_BUF (Note 7)
t_SU:WPA
(Note 7)
Clock Frequency
Clock High Time
Clock Low Time
Start Condition Setup Time
Start Condition Hold Time
Stop Condition Setup Time
SDA Data Input Setup Time
SDA Data Input Hold Time
SCL and SDA Rise Time
SCL and SDA Fall Time
SCL Low to SDA Data Output Valid Time
SDA Data Output Hold Time
Pulse Width Suppression Time at SCL and SDA inputs
Bus Free Time (Prior to Any Transmission)
A0, A1, A2 and WP Setup Time
t_HD:WPA
(Note 7)
A0, A1, A2 and WP Hold Time
V_CC x 0.1 to V_CC x 0.9
10ns
V_CC x 0.5
2.3k to V_CC and 100pF to V_SS
MIN
600
1300
600
600
600
100
30
0
1200
600
600
MAX
400
300
300
0.9
50
UNITS
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
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5
FN8167.3
July 24, 2014