X9252_14 Datasheet, PDF (12/19 Pages) Intersil Corporation – Quad Digitally-Controlled Potentiometer

X9252
TABLE 2. REGISTER NUMBERING
STATUS REG (Note 13) (Addr: 07H)
REGISTERED SELECTED (Note 14)
RESERVED
BITS 7-3
DRSel1
BIT-2
DRSel0
BIT-1
NVEnable
BIT-0
DCP0
(ADDR: 00h)
DCP1
(ADDR: 01h)
DCP2
(ADDR: 02h)
DCP3
(ADDR: 03h)
Reserved
X
X
0
WCR0
WCR1
WCR2
WCR3
0
0
1
DR00
DR10
DR20
DR30
0
1
1
DR01
DR11
DR21
DR31
1
0
1
DR02
DR12
DR22
DR32
1
1
1
DR03
DR13
DR23
DR33
To read or write the contents of a single Data Register or Wiper Register:
13. Load the status register (using a write command) to select the row (see Figure 6)
Writing a 1, 3, 5, or 7 to the Status Register specifies that the subsequent read or write command will access a Data Register. This status register
operation also initiates a transfer of the contents of the selected data register to its associated WCR for all DCPs. So, for example, writing ‘03h’
to the status register causes the value in DR01 to move to WCR0, DR11 to move to WCR1, DR21 to move to WCR2, and DR31 to move to
WCR3.
Writing a 0 to bit ‘0’ of the status register specifies that the subsequent read or write command will access a wiper counter register. Each WCR
can be written to individually, without affecting the contents of any other.
14. Access the desired DR or WCR using a new write or read command (see Figure 7 for write and Figure 9 for read.)
Specify the desired column (DCP number) by sending the DCP address as part of this read or write command.
SIGNALS FROM
THE MASTER
SIGNAL AT SDA
SIGNALS FROM
THE SLAVE
If Bit-0 of data byte = 1,
DR contents move to WCR
during this ACK period
S
T
A
SLAVE
R
ADDRESS
T
S
STATUS REGISTER
DR SELECT
T
ADDRESS
DATA
O
P
0101
0 00000111
00000x x1
A
A
A
C
C
C
K
K
K
FIGURE 6. STATUS REGISTER WRITE (USES STANDARD BYTE WRITE SEQUENCE TO SET UP ACCESS TO A DATA REGISTER)
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FN8167.3
July 24, 2014