X9252_14 Datasheet, PDF (13/19 Pages) Intersil Corporation – Quad Digitally-Controlled Potentiometer

X9252
DCP Addressing for 2-Wire Interface
Once the register number has been selected by a 2-wire
instruction, then the DCP number is determined by the
Address Byte of the following instruction. Note again that this
enables a complete page write of the DRs of all four
potentiometers at once. The register addresses accessible
in the X9252 include:
TABLE 3. 2-WIRE INTERFACE ADDRESS BYTE
ADDRESS (HEX)
CONTENTS
0
DCP 0
1
DCP 1
2
DCP 2
3
DCP 3
4
Not Used
5
Not Used
6
Not Used
7
Status Register
All other address bits in the Address Byte must be set to “0”
during 2-wire write operations and their value should be
ignored when read.
Byte Write Operation
For any Byte Write operation, the X9252 requires the Slave
Address byte, an Address Byte, and a Data Byte
(see Figure 7). After each of them, the X9252 responds with
an ACK. The master then terminates the transfer by
generating a STOP condition. At this time, if the write
operation is to a volatile register (WCR, or SR), the X9252 is
ready for the next read or write operation. If the write
operation is to a nonvolatile register (DR), and the WP pin is
high, the X9252 begins the internal write cycle to the
nonvolatile memory. During the internal nonvolatile write
cycle, the X9252 does not respond to any requests from the
master. The SDA output is at high impedance.
The SR bits and WP pin determine the register being
accessed through the 2-wire interface (see Table 2).
As noted before, any write operation to a Data Register
(DR), also transfers the contents of all the data registers in
that row to their corresponding WCR.
For example, to write 3Ahex to the Data Register 1 of DCP2
the following sequence is required:
START
Slave Address 0101 0000
ACK
(Hardware Address = 000,
and a Write Command)
Address Byte
ACK
0000 0111
(Indicates Status Register
Address)
Data Byte
ACK
0000 0011
(Data Register 1 and
NVEnable Selected)
Note: at this ACK, the WCRs are all updated with their respective DR.
STOP
START
Slave Address
ACK
Address Byte
ACK
Data Byte
ACK
STOP
0101 0000
0000 0010
0011 1010
(Hardware Address = 000,
Write Command)
(Access DCP2)
(Write Data Byte 3Ah)
During the sequence of this example, WP pin must be high,
and A0, A1, and A2 pins must be low. When completed, the
DR21 register and the WCR2 will be set to 3Ah and the other
Data Register in Row 1 will transfer their other contents to
the respective WCR’s
SIGNALS FROM
THE MASTER
WRITE
S
T
A
SLAVE
R
ADDRESS
T
ADDRESS
BYTE
DATA
BYTE
S
T
O
P
SIGNAL AT SDA
01 01
0
SIGNALS FROM
THE SLAVE
A
A
A
C
C
C
K
K
K
FIGURE 7. BYTE WRITE SEQUENCE
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FN8167.3
July 24, 2014