X9252_14 Datasheet, PDF (2/19 Pages) Intersil Corporation – Quad Digitally-Controlled Potentiometer

X9252
Ordering Information
PART
NUMBER
(Notes 1, 2)
X9252YV24IZ-2.7
PART
MARKING
X9252YV ZG
R_TOTAL
(k)
2.8
TEMP RANGE
(°C)
PACKAGE
(Pb-free)
-40 to +85 24 Ld TSSOP (4.4mm)
PKG.
DWG. #
M24.173
X9252WV24IZ-2.7
X9252WV ZG
10
-40 to +85 24 Ld TSSOP (4.4mm) M24.173
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC
J STD-020.
2. For Moisture Sensitivity Level (MSL), please see device information page for X9252. For more information on MSL please see tech brief TB363
Functional Diagram
V_CC
A2
A1
A0
SDA
SCL
DS0
2-Wire
Interface
Up-Down
Interface
POWER-UP,
INTERFACE
CONTROL
AND
STATUS
R_H0
R_H1
R_H2
R_H3
WCR0
DR00
DR01
DR02
DR03
DCP0
WCR1
DR10
DR11
DR12
DR13
DCP1
WCR2
DR20
DR21
DR22
DR23
DCP2
WCR3
DR30
DR31
DR32
DR33
DCP3
DS1
CS
U/D
V_SS
WP
R_W0 R_L0
R_W1 R_L1
R_W2 R_L2
R_W3 R_L3
Pin Descriptions
PIN #
1, 24
2, 14, 11
3
4
5
6
7
8
9
10
12
13
15
16
17
18
SYMBOL
DS0, DS1
A0, A1, A2
R_W3
R_H3
R_L3
U/D
V_CC
R_L0
R_H0
R_W0
WP
SDA
R_L1
R_H1
R_W1
V_SS
DESCRIPTION
DCP select for Up/Down interface.
Device address for 2-wire bus.
Wiper terminal of DCP3.
High terminal of DCP3.
Low terminal of DCP3.
Increment/decrement for up/down interface.
System supply voltage
Low terminal of DCP0.
High terminal of DCP0.
Wiper terminal of DCP0.
Hardware write protect
Serial data input/output for 2-wire bus.
Low terminal of DCP1.
High terminal of DCP1.
Wiper terminal DCP1.
System ground
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FN8167.3
July 24, 2014