X9252_14 Datasheet, PDF (6/19 Pages) Intersil Corporation – Quad Digitally-Controlled Potentiometer

SDA vs SCL Timing
SCL
t_SU:STA
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
X9252
t_F
t_HIGH
t_SU:DAT
t_HD:STA
t_LOW
t_R
t_HD:DAT
t_AA t_DH
WP, A0, A1, and A2 Pin Timing
START
SCL
Clk 1
STOP
SDA IN
WP, A0, A1, or A2
t_SU:WP
t_HD:WP
t_SU:STO
t_BUF
Increment/Decrement Timing
SYMBOL
PARAMETER
t_CI
t_ID (Note 7)
t_DI (Note 7)
t_IL
t_IH
t_IC
t_CPHS
t_CPHNS
(Note 7)
CS to SCL Setup
SCL HIGH to U/D, DS0 or DS1 Change
U/D, DS0 or DS1 to SCL Setup
SCL LOW Period
SCL HIGH Period
SCL Inactive to CS Inactive (Nonvolatile Store Setup Time)
CS Deselect Time (Store)
CS Deselect Time (No Store)
t_IW (Note 7) SCL to R_W Change
t_CYC
SCL Cycle Time
t_R, t_F (Note 7) SCL Input Rise and Fall Time
MIN
TYP (Note 6)
MAX
600
600
600
2.5
2.5
1
10
1
100
500
5
500
UNITS
ns
ns
ns
µs
µs
µs
ms
µs
µs
µs
µs
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6
FN8167.3
July 24, 2014