X28C512_06 Datasheet, PDF (8/21 Pages) Intersil Corporation – 5V, Byte Alterable EEPROM

X28C512, X28C513
Software Data Protection
V_CC
0V
Data
Addr
AAA
5555
CE
55
2AAA
WE
A0
5555
≤ t_{BLC MAX}
Writes
ok
t_WC
Byte
or
Page
(V_CC)
Write
Protected
Note: All other timings and control pins are per page write timing requirements
FIGURE 4A. TIMING SEQUENCE—SOFTWARE DATA PROTECT ENABLE SEQUENCE FOLLOWED BY BYTE OR PAGE WRITE
Write Data AA
to Address
5555
Write Data 55
to Address
2AAA
Write Data 80
to Address
5555
Write Data XX
to any
Address
Write Last
Byte to
Last Address
Optional
Byte/Page
Load Operation
Software Algorithm
Selecting the software data protection mode requires the
host system to precede data write operations by a series of
three write operations to three specific addresses. Refer to
Figures 4A and 4B for the sequence. The three byte
sequence opens the page write window, enabling the host to
write from one to one hundred twenty-eight bytes of data.
Once the page load cycle has been completed, the device
will automatically be returned to the data protected state.
Regardless of whether the device has previously been
protected or not, once the software data protected algorithm
is used and data has been written, the X28C512, X28C513
will automatically disable further writes, unless another
command is issued to cancel it. If no further commands are
issued the X28C512, X28C513 will be write-protected during
power-down and after any subsequent power-up. The state
of A₁₅ while executing the algorithm is “don’t care”.
Note: Once initiated, the sequence of write operations
should not be interrupted.
After t_WC
Re-Enters Data
Protected State
FIGURE 4B. WRITE SEQUENCE FOR SOFTWARE DATA
PROTECTION
8
FN8106.2
June 7, 2006