English
Language : 

X28C512_06 Datasheet, PDF (4/21 Pages) Intersil Corporation – 5V, Byte Alterable EEPROM
◁
Pinouts
X28C512, X28C513
Plastic DIP
CERDIP
FLAT Pack
SOIC (R)
NC 1
NC 2
32 VCC
31 WE
A15
3
30 NC
A12
4
29 A14
A7
5
28 A13
A6
6
27 A8
A5
7
26 A9
A4
8 X28C512 25
A11
A3
9
24 OE
A2
10
23 A10
A1
11
22 CE
A0
12
I/O0
13
I/O1
14
I/O2
15
VSS
16
21 I/O5
20 I/O4
19 I/O3
18 I/O2
17 I/O1
PGA
I/O0 I/O 2 I/O 3 I/O 5 I/O 6
15
17
19 21
22
A1
13
A0
I/O 1 VSS I/O 4 I/O 7 CE
14
16
18 20
23
24
A2
12
A3
11
A10 OE
25
26
A4
A5
10
9
A6
A7
8
7
Bottom
View
A11 A9
27
28
A8
A13
29
30
A12
A15 NC
VCC NC
NC
A14
6
5
2
36 34
32
31
NC NC NC WE NC
4
3
1
35
33
Pin Descriptions
Addresses (A0-A15)
The Address inputs select an 8-bit memory location during a
read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/write
operations. When CE is HIGH, power consumption is
reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers and
is used to initiate read operations.
Data In/Data Out (I/O0-I/O7)
Data is written to or read from the X28C512, X28C513
through the I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28C512, X28C513.
Pin Names
SYMBOL
A0-A15
I/O0-I/O7
WE
CE
OE
VCC
VSS
NC
PLCC/LCC
30
A7
54 3 2
32 31 29
A14
A6 6
1
28 A13
A5 7
27 A8
A4
A3
8 X28C512 26
9 (Top View) 25
A9
A11
A2 10
24 OE
A1 11
23 A10
A0 12
22 CE
I/O0
13
14
15 16 17 18 19 20 21
I/O7
30
A6
54 3 2
32 31 29
A8
A5 6
1
28 A9
A4 7
27 A11
A3
A2
8 X28C513 26
9 (Top View) 25
NC
OE
A1 10
24 A10
A0 11
23 CE
NC 12
22 I/O7
I/O0
13
14
15 16 17 18 19 20 21
I/O6
DESCRIPTION
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
Ground
No Connect
4
FN8106.2
June 7, 2006
 ▷